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From the 8085 CPU architecture, when ALU done calculation, the result is clocked back to accumulator A on next clock edge. But accumulator A is directly wired as ALU input, what if the clock edge didn't raise fast enough to cause A is being added twice or many more times, it would be extreme difficult to detect such an error, such a design is very "fragile" to me.

Unless, there is an extra register within ALU to temporary save ALU results?

https://en.wikipedia.org/wiki/Intel_8085#/media/File:Intel_8085_arch.svg

https://en.wikipedia.org/wiki/Intel_8085

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    \$\begingroup\$ This looks like a question for @KenShirriff… \$\endgroup\$ – duskwuff Mar 23 '17 at 20:18
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    \$\begingroup\$ Why do you think that clocking the ALU result in to an intermediate register wouldn't have the same possible issues as clocking it in to the accumulator? Either way, you had better know that your ALU produces a valid result with sufficient setup and hold time relative to the clock. \$\endgroup\$ – The Photon Mar 23 '17 at 20:46
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As @duskwuff suspected, I've looked into this. To answer the question, the 8085 has two extra registers in the ALU.

The 8085 has several "hidden" registers: a 16-bit WZ pair and two 8-bit ALU helper registers: ACT and TMP. WZ is part of the register file, while ACT, A (accumulator) and TMP are located in the ALU circuitry itself.

Here's a diagram of how the ALU works:

Register structure of the 8085's ALU

The ACT register has several important functions. First, it holds the input to the ALU. This allows the results from the ALU to be written back to the accumulator without disturbing the input, which would cause instability. Second, the ACT can hold constant values (e.g. for incrementing or decrementing, or decimal adjustment) without affecting the accumulator. Finally, the ACT allows ALU operations that don't use the accumulator.

One interesting consequence of the 8085's ALU setup is that a value can be loaded into the accumulator only after passing through the ALU.

Details on the 8085 register set are here and details of the ALU are here.

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    \$\begingroup\$ Somehow, I knew you would have something to say about this. :3 \$\endgroup\$ – duskwuff Mar 23 '17 at 21:56
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    \$\begingroup\$ brilliant ~ (both Ken Shirriff's blog and 8085)! \$\endgroup\$ – Ale Mar 23 '17 at 23:12
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In synchronous designs it is an important task of designer to ensure such things do not happen. Register, which is having data being "clocked" into, is having specific dynamic properties like clock raise time, clock hold time, data stable prior and after clock signal change. If timing is violated, resulting state is not guaranteed.

In your particular case ALU is having its propagation delay, and to add A twice there should be a time until new A is added to previous A within the adder and result appears at its output. Most probably it was simulated and calculated that such thing will not happen within defined allowed clock frequency range for the device. That's why datasheet explicitly has minimal and maximal clock ratings. For 8085A-2 it says:

  • Minimal CLK cycle period: 320 ns
  • Maximal CLK cycle period: 2000 ns
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The accumulator is the ALU's output register.

The 8085 has a two phase clock. Where single clock instruction like a NOP took 2 clock cycles. Similar to the 8088 used in the original IBM PC, the 8088 had a 4Mhz four phase clock and executed instruction at a rate of 1Mhz.

With the two phase clock you have two oscillator cycles for each instruction cycle.

Internally, for timing, any edge of either clock can be used. The clocks are inverted so there are actually four clocks available for timing.

Then you have transparent latches that latch on the falling edge and D-Flip Flops that latch on the rising clock edge.

A transparent latch allows the input data to propagate through to the output beginning at the clock's rising edge, and the values are latch on the falling edge of the clock.

The 8085 had many options when it came to avoiding propagation race conditions.

enter image description here

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  • \$\begingroup\$ "the 8088 had a 4Mhz four phase clock and executed instruction at a rate of 1Mhz" - the 8088 only has a single clock input pin (although it does expect a non-symmetric clock, with the high state lasting roughly twice as long as the low state, which indicates internally it is clearly doing different things in these states, unlike most modern processors that always clock everything on the same clock edge), so is this 4 phase clock generated internally somehow? Is there a description somewhere of how this works? \$\endgroup\$ – Jules Oct 13 '18 at 19:17

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