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I am a newbie to design of digital systems. I understand that Vivado HLS is a tool that accelerates the design productivity by allowing to check designs by checking them through an HDL. What does Vivado HLS to achieve this? What is the process that it goes through? What does it do in comparison to SDSoc?

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Vivado HLS lets you generate code in a hardware description language from a high level language, for example C or C++.

SDSoC can be seen as Vivado HLS with etra functionality, e.g., the possibility to combine the developed hardware with a Zynq and Linux running on the ARM cores. Furthermore, it offer additional analysis opportunities, for example to improve the throughput between RAM and hardware accelerator.

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