Currently, I am working with the DDS core on Vivado, using Verilog, to generate a sign wave using a phase width of 7 and output width of 12. I understand that DDS formats the output in 2's complement / signed decimal. However, I am required to output only unsigned decimal through a DAC module.

The current unsigned decimal sine wave looks like this:
enter image description here

Desired output (currently in signed decimal):
enter image description here

What is the best way for me to offset the 2s complement output data to be just positive values from 0 to AMPLITUDE?

  • 1
    \$\begingroup\$ Just invert the MSB, or what am I missing? It's equivalent of adding 2^(n-1). \$\endgroup\$
    – pipe
    Mar 24, 2017 at 12:40

1 Answer 1


Add an offset of amplitude / 2.


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