Currently, I am working with the DDS core on Vivado, using Verilog, to generate a sign wave using a phase width of 7 and output width of 12. I understand that DDS formats the output in 2's complement / signed decimal. However, I am required to output only unsigned decimal through a DAC module.
The current unsigned decimal sine wave looks like this:
Desired output (currently in signed decimal):
What is the best way for me to offset the 2s complement output data to be just positive values from 0 to AMPLITUDE?
