verilog packed v unpacked array error

Question

I'm new to verilog.

I'm trying to implement a 2:1 multiplexer on a FPGA development board (DE1-SOC altera) using built in switches and LEDs.

The following are the assignments that I'm using for the multiplexer, these pins are connected from the FPGA to the switches and leds on the dev board:

I'm getting this error on output LEDR[0];

declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions

I've googled unpacked v packed arrays but I cannot understand what is the issue, I just want to set this pin as an output.

SW[0] - select
SW[1] - input 1
SW[2] - input 2
LEDR[0] - output

This is the verilog

module ligths (SW[0], SW[1], SW[2], LEDR[0]);

input SW[0], SW[1], SW[2];

output LEDR[0];

assign LEDR[0] = ((SW[2] & SW[0]) | (SW[1] & ~SW[0]));  

endmodule 

Answer 1

While Alex's answer is correct about the solution, the reason for the error specifically is that you are trying to define a 2D (unpacked) array as an input port which is only supported by SystemVerilog.

Two examples. Unpacked:

input unpacked [5:0];

Packed:

input [5:0] packed;

The former example is an array of six 1-bit signals. The latter example is an array of one 6-bit signal. There is a very distinct difference.

The following should get rid of the unpacked/packed error:

input [0] SW, [1] SW, [2] SW;

However as you can see it is just ugly. Additionally depending on how smart the compiler is, you may end up with errors about redefinition of the signal SW instead.

Instead you would use Alex's approach of:

input [2:0] SW;

Answer 2

You need to specify the inputs and outputs as complete arrays, like so:

module ligths (SW, LEDR);
input wire [2:0] SW;
output wire LEDR;

Answer 3

I agree with both Tom's and Alex's solutions. But I think there're some issues haven't pointed out yet.

In Verilog, there's no packed or unpacked arrays. There're only vectors, scalars and array of vectors and scalars. In Verilog, port declaration can NOT be any array. That's why Alex's solution is true Verilog way.

module ligths (SW, LEDR);
  input wire [2:0] SW;
  output wire LEDR;

Port declaration always in format (IEEE 1364-2005, Verilog Standard)

nout_declaration ::= (From A.2.1.2)
    inout [ net_type ] [ signed ] [ range ] list_of_port_identifiers 
input_declaration ::= 
    input [ net_type ] [ signed ] [ range ] list_of_port_identifiers 
output_declaration ::= 
    output [ net_type ] [ signed ] [ range ] list_of_port_identifiers 
    | output reg [ signed ] [ range ] list_of_variable_port_identifiers 
    | output output_variable_type list_of_variable_port_identifiers 
list_of_port_identifiers ::= (From A.2.3)
    port_identifier { , port_identifier } 

For tools support Verilog greater than 95, you can also define port in port list.

module ligths (input [2:0] SW, output LEDR);

Another suggestion is meaningful name in code is recommended. Such as,

module mux (input sel, input d0, input d1, output out);

So, the port list and port declaration in the following code were wrong in Verilog.

module ligths (SW[0], SW[1], SW[2], LEDR[0]);
input SW[0], SW[1], SW[2];   
output LEDR[0];   
assign LEDR[0] = ((SW[2] & SW[0]) | (SW[1] & ~SW[0]));      
endmodule 

In SystemVerilog, the Packed Array and Unpacked Array are introduced, as well as the Unpacked Array Port. The difference is the range specified on left or right of the identifiers (variable names). Vectors in Verilog can be considered in the Packed Array category, and Array in Verilog can be considered in the category of Unpacked Array.

The Unpacked Array Port list as example in Section 23.3.3.5 Unpacked array ports and arrays of instances in IEEE 1800-2015, SystemVerilog Standard. But not compliant with the syntax definition (IEEE 1800-2015, SystemVerilog Standard)

inout_declaration ::= // from A.2.1.2
    inout net_port_type list_of_port_identifiers 
input_declaration ::=
    input net_port_type list_of_port_identifiers 
    | input variable_port_type list_of_variable_identifiers 
output_declaration ::= 
    output net_port_type list_of_port_identifiers 
    | output variable_port_type list_of_variable_port_identifiers 
ref_declaration ::= ref variable_port_type list_of_variable_identifiers 

In my experience, not all tools support it.

SystemVerilog also introduced a way to define fixed-size Unpacked Array with size in addition to define it with only range.

int Array[0:7][0:31]; // array declaration using ranges
int Array[8][32]; // array declaration using sizes

So, The following code actually means, declare the array SW with size 0, 1, and 2. Besides it's not what you intended. This violate another rule Once a name is used in a port declaration, it shall not be declared again in another port declaration or in a data type declaration

input SW[0], SW[1], SW[2]; 

Array in Verilog and SystemVerilog is an aggregated data type, which makes more meaning to Simulator than Synthesis Tools. As a designer, I would recommend the idea of Vector and Scalar in Verilog is enough. Advanced data structure is for verification. Try to restrict the usage of basic data structure in Verilog in design is always good practice.