Olin has been clear, but I would add some details about the Pulsed Latch Register, and why this architecture may have different Hold Time requirements respect to other flip-flops.
First: the difference between latch and flip-flop
As you probably know, a latch is a circuit which in the basic form has an input, an output and a clock; when the clock is at a certain value - say high, for a positive latch - the latch is transparent, which means that the output replicates the input. When the clock is at the other level - low in this case - the output is held at the value it was before the clock commuted.
The flip-flop has the same pin configuration, but has a difference: it holds the value with the clock both high and low, and samples the new value on the edge (positive or negative) of the clock.
Pulsed latch flip-flop
A pulsed-latch flip-flop is nothing else than a normal latch, where the clock is driven by a very short pulse; in this way, the time in which the latch is transparent is very short, and it in facts behaves like a flip-flop.
Moreover, if a circuitry is used to create the pulse from a normal square wave clock, the whole circuit behaves really as a flip-flop.
Hold time violation
The problem is that if you have a certain technology process, you will have more or less a maximum speed at which you can commute a signal, due to the conductivity of the driving gate and the input capacity of the following one. If you consider a pulsed latch, the pulsing signal will commute to the transparent value, stay in that level for satisfying the setup time of the latch, and then commute again in a time that constitutes the hold time.
So the time in which the input must be held in order to sample it properly is equal to the duration of the pulse corresponding to the sampling, which is about double the time required by the edge triggering flip-flop. Hence the increase in the hold time violations