I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like:
For latch, "...data must be held for a longer period of time, increasing the likely number of hold time violations".
Please explain what hold time violation is in the context of Latches.
A edge-triggered latch (flipflop) ideally samples the data line instantaneously on one of the edges of the clock. However, nothing is truly instantaneous, so the data must be valid for some finite amount of time around the clock edge. The time it must be fixed before the clock edge is called the setup time, and the time it must be fixed after the clock edge is called the hold time.
Hold time violation is a violation of the hold time requirement. If the datasheet says the minimum required hold time is 10 ns and you change the data 5 ns after the clock edge, then you have committed a hold time violation and there is no guarantee which data value will end up on the flipflop output.
Olin has been clear, but I would add some details about the Pulsed Latch Register, and why this architecture may have different Hold Time requirements respect to other flip-flops.
As you probably know, a latch is a circuit which in the basic form has an input, an output and a clock; when the clock is at a certain value - say high, for a positive latch - the latch is transparent, which means that the output replicates the input. When the clock is at the other level - low in this case - the output is held at the value it was before the clock commuted.
The flip-flop has the same pin configuration, but has a difference: it holds the value with the clock both high and low, and samples the new value on the edge (positive or negative) of the clock.
A pulsed-latch flip-flop is nothing else than a normal latch, where the clock is driven by a very short pulse; in this way, the time in which the latch is transparent is very short, and it in facts behaves like a flip-flop.
Moreover, if a circuitry is used to create the pulse from a normal square wave clock, the whole circuit behaves really as a flip-flop.
The problem is that if you have a certain technology process, you will have more or less a maximum speed at which you can commute a signal, due to the conductivity of the driving gate and the input capacity of the following one. If you consider a pulsed latch, the pulsing signal will commute to the transparent value, stay in that level for satisfying the setup time of the latch, and then commute again in a time that constitutes the hold time.
So the time in which the input must be held in order to sample it properly is equal to the duration of the pulse corresponding to the sampling, which is about double the time required by the edge triggering flip-flop. Hence the increase in the hold time violations
In a typical latching circuit (flip flop, latch, or combination of gates which exhibit latching behavior), when the clock or latch-enable input changes state, there exists a certain window during which the device will capture the state of the inputs. Any changes to the inputs before the start of that window will affect the outputs; changes after the end of that window will not. The start of the window is marked by the "setup time"; the end of the window is marked by the "hold time". If the input changes during the window, and the output is expected to reflect the new state, such a condition is generally called a "setup time violation". If the input changes during the window and the output is expected to reflect the old state, the condition is generally called a "hold time violation". From a design perspective, the distinction is useful: setup-time violations are solved by making a signal arrive sooner relative to the clock (or making the clock arrive later); hold-time violations are solved by making the signal arrive later.
An important point not mentioned in other answers, though, is that while input changes that occur within the forbidden window might cause the latch output to change to the new value, or might be ignored, they may also cause the latch enter a nasty "metastable" state, resulting in unspecified behavior. A latch may specify, for example, that its output will be value 10ns after an input clock pulse, but such a guarantee will only hold in the absence of timing violations. If the input to a latch changes within the forbidden window, the output may take an arbitrarily long time to switch, or it may switch quickly but then--some arbitrary time later, spontaneously switch back. To use an analogy, imagine a bowling ball striking a pin. If it hits the pin cleanly, the pin will topple instantly. If the ball barely glances the pin, the pin may quickly regain an upright equilibrium. Either of the above conditions could easily be observed, with certainty, in less than a second. On the other hand, it's possible for the ball to strike the pin in such a way that it will wobble for awhile and then fall over, or wobble for awhile and then fall down; one might decide to only announce a 'down' pin when a pin is obviously down, or a 'missed' pin when it's clearly not going to fall, but there may be an arbitrary period of time during which neither possibility can be ruled out.
