# WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process

I received a warning like this:

WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <clkDiv/counter_1> has a constant value of 0 in block <DAC>. This FF/Latch will be trimmed during the optimization process.


Is there something wrong in my code? thanks!

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity DAC is
port(
CLK: in std_logic;
CLK2: inout std_logic;
CS: out std_logic;
MOSI: out std_logic
);
end DAC;

architecture behavioral of DAC is
signal reg : std_logic_vector (23 downto 0) :="100001100011100000000001";
signal counter_G : integer range 0 to 24 := 0;
signal CS_S : std_logic := '1';
signal mosi_S : std_logic := '0';
constant DELAY:integer := 2;
begin
clkDiv : entity work.ClockDivider(Behavioral)
generic map(DELAY => DELAY)
port map (CLK, CLK2);

Senddata : process(CLK2, counter_G)
begin
if falling_edge(CLK2) then
counter_G <= counter_G + 1;
if counter_G <24 then
CS_S <= '0';
mosi_S <= reg(23);
reg <= reg(22 downto 0) & reg(23);
else
CS_S <= '1';
counter_G <=0;
end if;
end if;
end process Senddata;

CS <= CS_S;
MOSI <= mosi_S;
end behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ClockDivider is
GENERIC (DELAY: integer := 16 );
PORT
(
CLK : in  STD_LOGIC;
CLK_OUT : out  STD_LOGIC := '0'
);
end ClockDivider;

architecture Behavioral of ClockDivider is
begin
process(CLK)
variable counter : integer range 0 to DELAY := 0;
begin
if(CLK'event AND CLK='1') then
counter := counter + 1;
if counter = DELAY / 2 then
CLK_OUT <= '0';
elsif counter = DELAY then
counter := 0;
CLK_OUT <= '1';
end if;
end if;
end process;
end Behavioral;

• I received a warning like this:FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. is there something wrong in my code? thanks! Mar 25, 2017 at 5:27
• You got the code for the clock divider module? Mar 25, 2017 at 6:14
• Issue is likely inside the clkDiv entity (ClockDivider). This may or may not be a real problem, depending on the design. One or more of the FF/Latch described by that HDL code always have the value 0 regardless of any input. If those are just extra bits in a generic clock prescaler that might be tolerable, but if they are important bits expected to be toggling, then your code does have a design problem. Impossible to tell without looking at the code. Mar 25, 2017 at 9:22
• The problem is in entity clkdiv so post that in your question. Also, don't put more question in a comment - edit your question and put it there. Please make those changes and we can help. Mar 25, 2017 at 9:30

Don't use an inout type for CLK2. Either use VHDL-2008, or use a temporary variable.

Then counter is likely to be reset to 0 every time the clock divider process triggers. Don't use variables like this: use signals instead. E.g.

architecture Behavioral of ClockDivider is
signal counter : natural range 0 to DELAY := 0;
begin
clk_div_proc: process(CLK)
begin
if rising_edge(CLK) then
if counter < DELAY then
counter <= counter + 1;
else
counter <= 0;
end if;
if counter < DELAY/2 then
CLK_OUT <= '1';
else
CLK_OUT <= '0';
end if;
end if;
end process;
end Behavioral;