I've written some HDL code to convert the frequency of the clock on FPGA (100MHz) to a freqency which is compatible with my VGA monitor (65MHz):
reg FLAG = 0; reg [26:0]count; always@(posedge clock) begin if(reset) count <= 'd0; else if(count==65000000) begin FLAG = 1; count <= 'd0; end else begin count <= count+1; FLAG=0; end end
The value of flag would keep changing from 0 to 1 with frquency of 65MHz, but that isin't apparenly working for me. Can someone point out the error here? Also, is there a better way to convert one clock frequency to another?