Converting 100MHz clock to 65MHz clock for VGA

I've written some HDL code to convert the frequency of the clock on FPGA (100MHz) to a freqency which is compatible with my VGA monitor (65MHz):

reg FLAG = 0;
reg [26:0]count;
always@(posedge clock)
begin
if(reset)
count <= 'd0;

else if(count==65000000)
begin
FLAG = 1;
count <= 'd0;
end
else
begin
count <= count+1;
FLAG=0;
end
end


The value of flag would keep changing from 0 to 1 with frquency of 65MHz, but that isin't apparenly working for me. Can someone point out the error here? Also, is there a better way to convert one clock frequency to another?

• You cannot make 65MHz from 100MHz with counters. You would have to count a fraction of the time. If you count once with a 100MHz counter, the output would already be at 50MHz. One way to obtain 65MHz is with a PLL that multiplies the freq. first and then divides to obtain the 65MHz. For example you could multiply 100MHz by 13, then divide by 20 and obtain 65MHz. – Claudio Avi Chami Mar 25 '17 at 12:53
• On the Artix specifically, you want to use a DCM (digital clock manager) module, which can multiply and divide frequencies by a large range of factors. 65/100 would be no problem at all. – Dave Tweed Mar 25 '17 at 13:07
• The resulting signal would be so bad that I don't even want to discuss it. Let's hope @DaveTweed writes an actual answer for you. – pipe Mar 25 '17 at 13:11
• Read the documentation: 7 Series FPGAs Clocking Resources User Guide (UG472). Apparently, they're now called "Clock Management Tiles". There will be a "Wizard" in Vivado to help you configure it. – Dave Tweed Mar 25 '17 at 13:35
• @pipe, you can't even do that because 65 MHz is more than half of 100 MHz. At least not without messing around with combinatorial logic on the 100 MHz clock. – The Photon Mar 25 '17 at 16:04