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I've written some HDL code to convert the frequency of the clock on FPGA (100MHz) to a freqency which is compatible with my VGA monitor (65MHz):

reg FLAG = 0;
reg [26:0]count;
always@(posedge clock)
begin
    if(reset)
    count <= 'd0;

    else if(count==65000000)
    begin
        FLAG = 1;
        count <= 'd0;
    end
    else
    begin
        count <= count+1;
        FLAG=0;
    end
end

The value of flag would keep changing from 0 to 1 with frquency of 65MHz, but that isin't apparenly working for me. Can someone point out the error here? Also, is there a better way to convert one clock frequency to another?

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    \$\begingroup\$ You cannot make 65MHz from 100MHz with counters. You would have to count a fraction of the time. If you count once with a 100MHz counter, the output would already be at 50MHz. One way to obtain 65MHz is with a PLL that multiplies the freq. first and then divides to obtain the 65MHz. For example you could multiply 100MHz by 13, then divide by 20 and obtain 65MHz. \$\endgroup\$ – Claudio Avi Chami Mar 25 '17 at 12:53
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    \$\begingroup\$ On the Artix specifically, you want to use a DCM (digital clock manager) module, which can multiply and divide frequencies by a large range of factors. 65/100 would be no problem at all. \$\endgroup\$ – Dave Tweed Mar 25 '17 at 13:07
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    \$\begingroup\$ The resulting signal would be so bad that I don't even want to discuss it. Let's hope @DaveTweed writes an actual answer for you. \$\endgroup\$ – pipe Mar 25 '17 at 13:11
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    \$\begingroup\$ Read the documentation: 7 Series FPGAs Clocking Resources User Guide (UG472). Apparently, they're now called "Clock Management Tiles". There will be a "Wizard" in Vivado to help you configure it. \$\endgroup\$ – Dave Tweed Mar 25 '17 at 13:35
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    \$\begingroup\$ @pipe, you can't even do that because 65 MHz is more than half of 100 MHz. At least not without messing around with combinatorial logic on the 100 MHz clock. \$\endgroup\$ – The Photon Mar 25 '17 at 16:04
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You're going to have to instantiate a DCM or PLL to do this. See the clocking section in the manual for the FPGA you're using for how to do this properly. You'll need to do something like 100 MHz / 10 * 65 / 10 = 65 MHz or perhaps 100 MHz * 13 / 20 = 65 MHz. You'll have to make sure to get the VCO operating in the proper frequency range.

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  • \$\begingroup\$ You have to make sure you do not pass the maximum limit of the DCM or the PLL, just read the UG472 for help. The best way to do this is using the guide that comes with Vivado to create the right block/settings. \$\endgroup\$ – FarhadA Mar 27 '17 at 13:05
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Answering my own question, I used the Clocking Wizard which is a part of Vivado, thanks to @Naz for pointing me in the right direction. Clocking Wizard creates a module for you and depending upon your specifications, you can generate any clock frequency from that module.

The Clocking Wizard can be found in Project Manger->IP Catalog->FPGA Features and Design->Clocking.

For further details regarding the correct usage of Clocking Wizard, I referred to the follwing link: http://gadgetfactory.net/learn/2017/02/22/fpga-clocking-clocking-wizard-in-xilinx-ise/#Run_the_clocking_wizard_to_generate_your_desired_clocks

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