Working with Spartan-6 LX9 clock

Question

I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the board by starting with an example from Xilinx's web site. The code can be found here. I couldn't fully figure out DCM part of the example, though. As I understand, this is some vendor-specific module that is used to shift clock phase etc. Basically, a module that adjusts the raw clock input. I couldn't find a documentation for that module for my LX9 board, and the closest one I found is for Spartan-3A (here). So I have few questions:

• Is there any documentation for that is generic or covers Spartan-6 LX9 board?
• Is using this module is absolutely necessary in this example? Is that possible to do the same thing easily w/o using that module?
• How people usually go about vendor specific things like clock? For example, if one wants to target both Altera FPGAs and Xilinx ones. What is the process to achieve that? Is it similar to ordinary C pre-processor typedefs etc?

Also, why is it now allowed to move assign LED[3:0] = led_count[26:23]; inside the always @ block? Is it because LED is a not a register variable? And how often that "code line" is getting executed then? In the book I am reading, everything usually goes into the always @ scope (but they don't work with specific output ports though).

Thank you very much for your help.

Answer 1

1. Is there any documentation for that is generic or covers Spartan-6 LX9 board?

   The DCM is fully contained within the FPGA chip. So it doesn't matter what board you have. The documentation will be based on what chip you have.

   For the Spartan-6 family, see the Spartan 6 Clocking Resources User Guide

2. Is using this module is absolutely necessary in this example? Is that possible to do the same thing easily w/o using that module?

   If you're just blinking LEDs, you probably don't need to use the DCM. Probably they used it because its a very complicated block and they specifically wanted to provide an example of using the DCM without much else in the way of complex logic to confuse things.

3. How people usually go about vendor specific things like clock? For example, if one wants to target both Altera FPGAs and Xilinx ones. What is the process to achieve that? Is it similar to ordinary C pre-processor typedefs etc?

   Unfortunately, complex hard cores like clock management is one of the areas where there's not much compatibility between vendors. You'll likely have to make significant code changes if you want a design using these features that is portable between two device families, whether they're from the same or different vendors.

   If you can simplify your interface so that you just have one input clock coming from off-chip, and a number of derived clocks that are distributed to the rest of your logic, the cleanest solution is probably to push all of the vendor-specific code into a single module that you can instantiate in your top-level code. Then you can just use a different "clock management" module depending which device you're targeting.

   If you want to do something like dynamically changing the phase relationship between various clocks, or switch between several choices of reference clock frequency, you probably have no choice but to re-code substantial chunks of logic for different target devices.

   Remember that in addition to the Verilog code, there will probably also be numerous constraints that need to be defined, and these will also need to be different for different devices.