1
\$\begingroup\$
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TOP is port
(  
    CLOCK: in std_logic;
    Rdata_ADC: in std_logic;

    CLK2_ADC : out std_logic;
    CS_ADC  : out Std_logic;
    CS_DAC  : out Std_logic;
    SCK_DAC  : out std_logic;
    Mosi_ADC : out std_logic;
    Mosi_DAC : out std_logic
);

end TOP;

architecture behavioral of Top is
    signal Send_S, CLK2: std_logic;
    signal MOSI_DAC_S: std_logic :='0';
    Signal CS_DAC_S: std_logic :='0';
    signal DOUT_VALUE: std_logic_vector (11 downto 0) :="000000000000";
begin

    A0: ENTITY work.ADC(behavioral) port map
        (CLK=> CLOCK, R_DATA=> Rdata_ADC, CS=> CS_ADC, MOSI=> Mosi_ADC,
       CLk2=> CLk2, SEND=> Send_S, Dout=> DOUT_VALUE);

    A1: entity work.DAC(behavioral) port map
        (SCK=> SCK_DAC, CS=> CS_DAC_S, MOSI=> MOSI_DAC_S, 
        CLK2=> CLK2, SEND=> SEND_S, Value=> DOUT_Value);

   CLK2_ADC <= CLK2;
   MOSI_DAC <= MOSI_DAC_S;
    CS_DAC <= CS_DAC_S;

End behavioral;

enter image description here

Why I get 'u' even after initial the signal MOSI_DAC_S and CS_DAC_S to '0'?

\$\endgroup\$
  • \$\begingroup\$ It comes about because you're assigning MOSI_DAC <= MOSI_DAC_S; and CS_DAC <= CS_DAC_S;. You defined an initial value for the inner signals but there is one for the actual signals connected via a port map. These don't have initial values. They don't get updated until events on the right hand side signals. There is no guarantee of execution order between concurrent statements. \$\endgroup\$ – user8352 Mar 27 '17 at 1:10
  • \$\begingroup\$ Don't go around putting default values on signals, though. Never use default values in synthesizable VHDL (except in rare cases), it gives misleading results and reduces portability. Implement a proper reset scheme instead, taken from an externally or internally generated reset source. \$\endgroup\$ – TonyM Mar 27 '17 at 8:06
  • \$\begingroup\$ @TonyM Is there an FPGA tool chain that doesn't support initial values? Not everyone is in a position where they need to worry about their design being ported into an ASIC flow. \$\endgroup\$ – scary_jeff Mar 27 '17 at 9:34
  • \$\begingroup\$ @scary_jeff yes, lots of CPLDs as well as many Microsemi and Lattice parts. Who said ASICs? Not everyone is using RAM-based FPGAs. I design into a very wide range of devices for different projects. Don't use initial values in synthesizable logic. Fine for testbenches only. \$\endgroup\$ – TonyM Mar 27 '17 at 9:38
  • \$\begingroup\$ @TonyM OK, what are the rare cases where you can use them? \$\endgroup\$ – scary_jeff Mar 27 '17 at 9:44
2
\$\begingroup\$

You have 'U' on the wires because it connected from internal module and probably appropriate signals weren't initialize there. So if you initialize the signals in internal module you will not get 'U'.
You have to initialize signals which connected to CS and MOSI outputs in module DAC.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.