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I have quite precise ADC circuit. I want to protect input supply voltage (not ADC input) from reverse-polarity using FET transistor as shown on the picture below.

I wonder: is there any noise / worse performance introduced in ADC measurements due to use of FET on the power line? Power supply is also reference voltage for ADC. The alternative for me is just not use any re-pol. protection.

enter image description here

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  • \$\begingroup\$ This is impossible to answer without knowing anything about your ADC circuit. Maybe the ADC is very insensitive to supply noise. Maybe the supply decoupling will filter out the noise. \$\endgroup\$ – Bimpelrekkie Mar 27 '17 at 10:38
  • \$\begingroup\$ I'm afraid you haven't shown us the very part of the circuit you're asking about. Please can you modify the question to show this, the more the better (up to a point). \$\endgroup\$ – TonyM Mar 27 '17 at 10:51
  • \$\begingroup\$ Well, actually I don't have ADC circuit yet, it's still an open case. I started thinking from power supply; I thought "it would be nice to protect the device from wrong battery placement", but then I thought "but will it make my ADC meas. worse?" - so the question is general: does non-switching transistor introduce any noise? Or is more like a resistor? \$\endgroup\$ – zupazt3 Mar 27 '17 at 11:39
  • \$\begingroup\$ More noise is going to come from your power supply and regulators first. Your MCU digital circuitry too if you use an onboard ADC. Deal with the worst offenders before dealing with the small fry. With 12-bits, it won't even matter. Plus the PFETs its at the input of the first regulator anyways. You're splitting hairs. \$\endgroup\$ – DKNguyen Feb 28 at 15:20
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Lets examine VDD sag, due to series FET switch and local bypass capacitor:

schematic

simulate this circuit – Schematic created using CircuitLab

The added resistance of FET switch will reduce the VDD to ADC, and to the VREF. Can you accept that?

The 100Ohm to ADC Ref pin causes an I*R error, because Ref pin demands charge as the ADC performs the analog-digital conversion. The average of that charge, over time, is a DC current flow; that current times 100Ohm is the Ref error.

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  • \$\begingroup\$ I don't think that FET will reduce VDD to ADC or VRef, as the FET will be placed before LDO voltage regulator. So it will decrease a bit voltage, but that doesn't matter as it is regulated later. Am I right? \$\endgroup\$ – zupazt3 Mar 27 '17 at 21:08
  • \$\begingroup\$ You are right. By the way, how many bits do you plan to use? And what sampling rate? And what is the minimum input level? Using the VDD as your reference to ADC will cause errors, unless the VDD is also used as reference to the Sensor, such as a voltage divider with one resistor a Thermistor, or a bridge for strain-gauges, etc. Does you sensor design include using the VDD as its reference? \$\endgroup\$ – analogsystemsrf Mar 28 '17 at 2:14
  • \$\begingroup\$ Well, at first I will use built-in ADC in STM32, so 12 bits at 2.4 MSPS powered with 3.3V. Later maybe I will add some ext. ADC. This is general purpose DAQ device, so "general purpose" means compromise between price and quality. But yes, sensors should use the same VDD as the main board. If user powers it differently, well, I think I cannot do a lot with it then. So the user will have to accept errors if powering it from different sources and only connecting GND. \$\endgroup\$ – zupazt3 Mar 28 '17 at 8:27
  • \$\begingroup\$ Part of your design task may be to provide a stable trustable voltage reference, say at 4.096 volts or 2.500 volts. \$\endgroup\$ – analogsystemsrf Mar 29 '17 at 17:00
  • \$\begingroup\$ Probably that will be needed. Btw. can you suggest any good voltage regulator and p-FET for this purpose? By good I mean good price / quality ratio with a little inclination towards price. \$\endgroup\$ – zupazt3 Mar 29 '17 at 17:53

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