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I am working on a project that involves a lot of switching of electromagnets.

The switching is controlled by a PIC32MX6xx-series microcontroller, which determines the required states of 80x 12 VDC electromagnets (each drawing about 15-200 mA) and outputs this data to a series of interconnected 74HC595 shift registers. These shift registers' outputs each switches a MOSFET on/off, which in turn switches its respective electromagnet.

The problem that I am experiencing is that, when the electromagnets are switched, the PIC resets intermittently. There is no particular switching sequence/load that causes this reset - it happens completely at random. At times it takes about 30 seconds of switching to reset it, and at some other times almost 15 minutes.

What I do know is that it is the MCLR-reset that takes place - I determined this by monitoring the RCON register, where the EXTR-flag bit (MCLR reset event) is set on each such reset. This is the initial circuit of the PIC, with specific focus on the MCLR-pin and the decoupling capacitors as recommended by the PIC's datasheet.

MCLR pin and decoupling capacitors

It can be seen from the diagram, that there is a 1k resistor between GND and the switch, as well as a 10k pull-up resistor on the MCLR-pin. After noting the recommendation of a capacitor at the MCLR-pin to prevent unintentional resets, I added a 100 nF ceramic capacitor between the MCLR-pin and GND. Yet still, the resets still occur intermittently, although it seems as if the interval between resets were longer than without the capacitor.

In the hope to eliminate the reset occurrence, I replaced the 1k resistor between the switch and GND, as well as the 10k resistor between the MCLR-pin and VDD with 0-ohm resistors (short circuits). This would ensure that the MCLR-pin is always connected to VDD. The 100 nF capacitor was also still present. Thus, essentially the only component connected to the MCLR-pin is the 100 nF capacitor between the MCLR-pin and GND. Yet still, the intermittent resets continue to occur.

The system is powered by an industrial transformer with a 380 VAC, 3-phase input and 12 VDC output. This 12 VDC output is then the input to two LM1085 voltage regulators - one with a 5 V output (powering all logic ICs) and the other a 3.3 V output (powering the PIC). A surge suppressing circuit consisting of a MOV and snubber diode is also in place right before the voltage regulator inputs (12 VDC inputs).

The MOSFET switch circuit for each electromagnet is as follows: Electromagnet switching circuit

As can be seen, the switching circuit is a high-side switching circuit (common negative) topology, using both an NMOS and PMOS transistor for the switching. Note that there is a snubber/flyback diode in place as well. The LED is purely there to indicate the state of the electromagnet. This is the circuit used for every electromagnet in the system.

Since the MCLR pin is an active-low signal, the only event that I can foresee that would trigger the reset event is if there is a momentary drop in VDD (since the MCLR pin is directly connected to VDD). However, since VDD is provided by an LM1085 voltage regulator, my guess would be that a sudden "positive" voltage spike on the 12 VDC supply wouldn't cause such a drop in the voltage regulator's output. Therefore, the only explanation that I can come up with is that the supply voltage is probably momentarily dropping to such a level that causes a low enough voltage on the VDD line that triggers the MCLR reset event, although I cannot quite figure out how that would happen. The only other possibility in my view could be that a voltage spike propagates on the GND signal, causing the voltage differential between VDD and GND to become small enough to be within the range considered as a LOW signal on the MCLR line, since the microcontroller's "ground" is momentarily above 0 V during the occurrence of the voltage spike.

Some answers to possible anticipated questions:

  • Connecting the flyback diodes directly to the electromagnets is not practical due to the location of the electromagnets. The flyback diodes are therefore placed together with the MOSFET switching circuit on the control circuitry PCB.
  • The outputs from the control circuitry are all terminated into a Krone block, where the electromagnets' positive signal lines are also terminated. The distance from the Krone block to the actual electromagnets is anything between 2 to 10 meters.
  • I currently do not have access to an oscilloscope in order to see what actually happens on the VDD and MCLR lines.

Given the precautions I've already taken against voltage spikes/surges, what am I still missing? It is absolutely crucial that the PIC doesn't reset intermittently as it currently does.

Inputs, advice and comments will be greatly appreciated.

Thank you in advance.

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    \$\begingroup\$ Is that output from the PIC tied DIRECTLY to the gate of that MOSFET? \$\endgroup\$ – Trevor_G Mar 27 '17 at 14:50
  • \$\begingroup\$ Superb question. \$\endgroup\$ – analogsystemsrf Mar 27 '17 at 15:55
  • \$\begingroup\$ @Trevor: No, it is the output of the shift register that is tied directly to the gate of the N-channel MOSFET. Is this a concern? \$\endgroup\$ – wave.jaco Mar 29 '17 at 10:05
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This strongly smells of the solenoid return currents and inductive kickback paths not being handled properly. There are large and fast voltage spikes at the solenoids. Sometimes one of these couples enough to the microcontroller to confuse its internal logic. The reset mechanism is being tripped, but not by the external MCLR pin.

Absolutely the first thing you must do is ADD A BYPASS CAP across the micro's power and ground pins! Put a 1 µF ceramic cap physically as close as possible between the power and ground pins. This is exactly the kind of symptom a lack of bypass cap would cause.

Other than that, there are two remaining obvious suspects: poorly designed power and return current paths, and poorly handled inductive kickbacks.

Your schematic doesn't give us any idea of the physical layout of the power and return currents to the solenoids. The current loop of power supply to solenoid and back to power supply should have as little in common as possible with the microcontroller power loop. For example, if the two share a significant section of a ground wire, then the high solenoid currents in that ground wire could cause a ground bounce for the micro.

Ideally, there are separate power and ground feeds to the solenoids and the digital circuitry, with these connected at only one place close to the power supply. Then of course there needs to be proper bypassing of the power at each point of use on the digital side.

You do have a diode that is supposed to catch the inductive kickback, but you haven't shown any specs. No, a 1N400x is not appropriate here. I'd rather see a Schottky diode, due to their very fast response times.

Placement of the diode is also important. It is good to have some protection at your driver circuit in case stuff happens, but to really deal with inductive kickback it should be shunted as close to the source as possible. You want to contain the nasty current in as small and local a loop as possible. Small minimizes its radiation and capacitive coupling to elsewhere. Local keeps it from causing ground bounces and the like to other parts of the circuit.

As a experiment, try adding Schottky diodes in reverse across each solenoid right at the solenoid. Perhaps you can't put them there in final production, but do the experiment anyway to see if things change.

I suspect by observing proper hygiene, things will work a lot better. After you fix this mess, reflect on all the times you were told to use bypass caps, carefully place return current paths, keep the loops small, etc, and you thought "bypass schmypass, blah, blah". Now you know why it matters. Yes, you can get away without this sometimes, but sooner or later it will catch up with you. It just did.

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  • \$\begingroup\$ Thanks very much for your answer, Olin. There are plenty of bypass caps as close as possible to the PIC's power and ground pins, as suggested by the datasheet. I am very sure that the bypass caps are sufficient, but I will just double-check. As per my previous replies to comments by other posters, one certain culprit is the use of common ground return paths (and power supply lines) to and from the solenoids. Separation of those is certainly one improvement to the system. I currently have 1N4007 diodes and will replace them with the Schottky diodes as per your suggestion. \$\endgroup\$ – wave.jaco Apr 25 '17 at 12:56
  • \$\begingroup\$ previous comment continued I am sure that I have a good idea of how to improve on the design around the ground and power supply lines. The trickiest part for me to properly grasp/solve is the handling of the inductive kickback. It is extremely difficult to get to the actual solenoids to add the diodes for an experiment. The best I can do is to build a small rig with similar solenoids and simulate the actual system and see what happens. Regarding your suggestion for the Schottky diodes, are these thus usually a much better choice than the standard 1N400x diodes for such an application? \$\endgroup\$ – wave.jaco Apr 25 '17 at 13:01
  • \$\begingroup\$ @wave: Schottky diodes are usually better for catching inductive kickback because of their fast response times. This is essential if PWM is used, where the current from the previous pulse is still flowing when a new pulse starts. 1N400x are way too slow for that. Due to the lower voltage drop of Schottkys they let the current circulate a little longer before dying out. That can slow down the off time of relays. The right size resistor in series takes care of that. Essentially you get a managed finite kickback voltage that way. \$\endgroup\$ – Olin Lathrop Apr 25 '17 at 14:28
  • \$\begingroup\$ I see what you mean with the Schottky diodes. In my case there is no PWM going on, but if a better diode can be used then it seems only logical to improve on the design in that aspect. I've looked at a few Schottky diodes' datasheets and the 1N5819 seems to be a suitable choice in my application. I have another question that I want to ask, but I will send you a chat message for that, since it deviates from this original question. \$\endgroup\$ – wave.jaco Apr 26 '17 at 6:59
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Lets examine your possibilities.

The PIC has a numerous reset paths with various register flags to indicate the source of the reset. MCLR is one of these. You have already tried tying the MCLR directly to the supply rail for the PIC, so you can rule out noise on that pin as the source of this event.

The PIC is also equipped with a power on reset that occurs if the power is removed and re-applied. I'm assuming by you saying that the EXTR flag is set that ONLY that flag is set, that is all the other flags are not set. As such you did not lose power on the chip.

Similarly, the power did not dip or the brown-out flag would be set.

So what does that leave us... The chip did something internally you can not explain.

What might cause that? The chip has an internal voltage regulator to drive it's internal circuitry and requires that C1 cap, The cap needs to be very close to the VCAP pin. I assume for now you followed those instructions.

So, assuming all the above is correct, and we know the reset occurs when you switch the solenoids, what might be happening?

You have not indicated in your drawings or text how the return path (grounds) for the solenoids are connected. However, the position of the fly-back diode D5, suggests the grounds are common between the load and the logic. That would be a mistake. The grounds from the solenoids need to go back to the 12V regulator via their own path, separate from the 5V ground system and the fly-back diode needs to be connected to that ground. Failure to do so can cause a significant spike, or offset, in the PICs ground which will do unpredictable things internally.

Since your lead lengths are so long I would also suggest adding a small snubber circuit (R-C) across the fly-back diode.

Further, looking at your driver circuit, I see no resistor to the gate of Q25.

MOSFETS have a significant capacitance at the gate to both the drain and the source. That means there will be a significant current spike on the 74HC595 output when you switch the MOSFET on and off. Further, when you turn it off, the drain will be close to 12V and the 74HC595 will have to pull that down form the gate-souce capacitor. How that ties back to the PIC and what that does to the internals of the PIC is indeterminate.

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  • \$\begingroup\$ Thanks for the answer. Unfortunately I did not check if any other flags besides the EXTR flag have been set after the reset. That is certainly something that I will have to double-check to be sure. The capacitor is about 12 mm from the VCAP-pin due to the routing of other pins' traces. As you pointed out, the grounds between the electromagnets and the logic are indeed common, which is indeed a red flag. About the snubber circuit at the flyback diode, what would a suitable time constant be for this? ** comment continued in new comment post after this one ** \$\endgroup\$ – wave.jaco Mar 29 '17 at 10:16
  • \$\begingroup\$ ** previous comment continued ** There is indeed no resistor at the gate of Q25. Your comment on this raises a possible explanation for another phenomenon - in some isolated cases, some transistors remained "on" after the 74HC595 outputs changed to 0 (off). When those particular electromagnets were to be switched on again, the NMOS transistors burnt out (The spec'ed max current for the NMOS transistors are 0.5 A, while the PMOS is spec'ed at 4.2 A). This is another problem I have yet to solve. I will start a separate thread on this soon and put the link in the original question. \$\endgroup\$ – wave.jaco Mar 29 '17 at 10:24
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    \$\begingroup\$ @wave.jaco The snubber RC will need to be at least *10 your mimimum switching time. Yes that small inline resistor helps provide a lot of isolation when dealing wit inductive loads that create rather uncomfortable spikes. It is probably prudent to add another one above the N-Channel to the gate of the P-Channel for the same reason. \$\endgroup\$ – Trevor_G Mar 29 '17 at 17:07
  • \$\begingroup\$ Thank you for the clarification on the snubber RC time constant. That inline resistor at the transistors might be just what is necessary to prevent the damaging of the transistors as I mentioned in my previous comment. I presume that it will also protect the 74HC595 from these spikes? In the cases where the transistors got damaged as I described, the respective 74HC595 was also fried. What would be a suitable value for this resistor? If I understand correctly, will this resistor just dissipate that charge release slower than it currently does (with the short circuit)? \$\endgroup\$ – wave.jaco Mar 30 '17 at 7:11
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    \$\begingroup\$ @wave.jaco yes the grounds should meet up somewhere prior to the U1 regulator. If there are long leads from the board back to the source though you may need more filtering on the input to the regulator.. bigger bulk and a fast bypass. WATCH for the offset to Vgd on the n-channel mosfet that ground separation will cause though. If it gets too much you may need to opto-isolate that. \$\endgroup\$ – Trevor_G Mar 30 '17 at 9:22
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At least 4 paths to upset the MCU (1) electric fields coupling to MR (2) magnetic fields coupling (3) VDD collapsing or VDD overvoltage (4) GND upset, what with FET return paths sharing GND with MCU

Lets address (4) first:

schematic

simulate this circuit – Schematic created using CircuitLab

Interesting, that a LOCAL BATTERY at the FET Drivers, using 1uH inductors in the 12volt line, with 0.03 ohm Rdampen, isolates the FET Driver trash. That 1uH needs to handle high current: 30 solenoids * 0.2amp = 6 amps.

Notice the Separation of GND between FET Drivers and MCU. By making the LOCAL BATTERY, the transient currents in GND are very small; the 1,000uF capacitor provides the surge currents; if switching a solenoid takes 10uS, at 0.2 amps, the VDD upset at FET Drivers is $$dV/dT = I/C$$ $$dV = I * T / C$$

$$dV = 0.2amp * 10uS / 0.001 Farad = 2e-6/1e-3 = 2 milliVolts$$

If the LOCAL BATTERY does not stop the resets, then a shield plate may help. To capture Efield charge injection, tie the shield with SHORT WIRE to MCU GROUND; are you using a Ground Plane under the MCU?

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What upset voltage, due to rapidly switched currents through MOSFETS? [ warning: this example is intended to upset you, to motivate you to attend to planning the PCB ( or multiple PCBs) and loops. ]

Suppose you have 0.2 amps, switching in 5 nanoSeconds. Flowing in a long wire. Magnetically coupling into a 0.1 meter * 0.1 meter (4 inches square) loop. What is the induced voltage, if Distance is 10cm (0.1 meter)?

Use the formula $$Vinduce = [MU0*MuR*Area/2*pi*Distance] * dI/dT$$

Area = 0.1*0.1 = 0.01Meter. Distance is 0.1 meter. Mu0 is 4*I*10^-7. The formula becomes $$Vinduce = 2e-7 * Area/Distance * dI/dT$$

Vinduce = 2e-7 * 0.01/0.1 * 40 Million Amps/second Vinduce = 2e-7 * 0.1 *40e+6 = 8 * e-7 * e+6 = 8 * e-1 = 0.8 volts.

Two FETS simultaneously switching: 1.6 volts Three FETS simultaneously switching: 2.4 volts

So lets revise the GND system:

schematic

simulate this circuit

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  • \$\begingroup\$ Thanks for the answer. As pointed out by Trevor, the shared grounds between the FET drivers/electromagnets and MCU is a very probable cause for the resets. Regarding the LOCAL BATTERY concept, do you suggest that I add the 1 uH inductor and 1000 uF for every 30 magnets? If the VDD upset (based on your calculations) is 2 mV per magnet, would that add up proportionally if multiple magnets are switched simultaneously? Also, what do you mean by the "surge currents" that the 1000 uF capacitor provides? There is a ground plane under the MCU. All of the "unused" surface on the PCB is a ground plane. \$\endgroup\$ – wave.jaco Mar 29 '17 at 10:36
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    \$\begingroup\$ The 1,000uF cap can supply all 100 solenoids, if you wish. Note the 0.03 ohm resistor, to left of the 1uH. That value is picked from sqrt(L/C) to dampen, to prevent ringing of that L+C. The long wires to the solenoids, at 1uH/meter (rule of thumb) are another cause of ringing. You can stagger the switching by using different values of resistors from the Shift Register to the FET gates; but delta_R of 100 Ohms * 1000pF of Cgate is only 100nanoseconds change in delay. Consider soldering a #22 wire in parallel with the existing Ground, to tie together various GND pieces. Yes, that 2mV adds up. \$\endgroup\$ – analogsystemsrf Mar 29 '17 at 17:12
  • \$\begingroup\$ Do I understand correctly that you mean the 1000 uF cap filters out the surge currents, rather than providing them? Thank you for the clarification on the 0.03 ohm resistor. I see your diagram says it is 100 ohm. Is this just a typo, or is this resistor there in addition to the 0.03 ohm resistor, thus a total of 100.03 ohm left of the 1 uH inductor? By "staggering the switching", do you mean adding resistors of various values to the FET gates to account for an average of the possible lengths of the wires to the electromagnets? I am not too sure what you mean by this "staggering". \$\endgroup\$ – wave.jaco Mar 30 '17 at 7:00
  • \$\begingroup\$ That resistor should be 0.03 ohms; thanks for mentioning that error. Regarding the surge currents, as the FETs abruptly provide current to the solenoids, we want the current transients to be locally supplied from the 1,000uF capacitor; the inductor is just a way to additionally encourage the transients to ONLY come from the 1,000uF; that 0.03 dampens the LC circuit. The DC current for solenoid will come through 0.03ohm+1uH. To stagger the switching, you can have the FETs switch with various delays, but your 100 control signals come from that shift-register. You'd need RC delays, plus Schmitts. \$\endgroup\$ – analogsystemsrf Mar 30 '17 at 10:54

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