DRAM processes are usually just mean that you have a trench capacitor with a high density pattern option. I know for a fact that those GF processes in your list have a trench capacitor, and I'm confident that the other 40nm or smaller nodes will as well. I use DRAM instead of SRAM when I need more than about 6MiB because the charge-amps required for SRAM end up using more power than the DRAM refresh.
As an example, this answer has an illustration of my work from a 14nm SOI process where I get about 8-bits DRAM per the area of a single FLASH gate (non-FLASH process), which is about the same area as the cost of 2-bits of SRAM.
Here's the kicker, you will need the NDAs to see what is actually in the design kits. For example, the GF 24nm white paper only lists a fraction of the devices that I see in the kit.