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I have not find a solution about between top overlay or bottom overlay and vias. Can you help me about this . I need identify a rule.I don't want the silkscreen to touch a via

enter image description here

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For this, if you do not wish to tent your vias, it is safe to assume that there will be a solder mask layer present on the vias and any other pad for that matter which I also assume you will not want silkscreen to cover.

If this is the case, the answer is pretty simple, simply set a rule in the "SilkToSolderMaskClearance" option. See image below.

enter image description here
This is found under the manufacturing section of the rule list. Then you can select to create a new rule, and you can set a custom query under the "Where The First Object Matches" to "IsVia" - you can leave this as "All" if you want the rule to apply to all exposed copper regions, and then "Where The Second Object Matches" -> Layer -> Top Overlay.
You can then select whether the clearance is from the exposed copper, or the Solder Mask opening and set the distance that you require. If it is for a straight overlap, set this to 0 and then it will only detect if it overlapping, not if it is close to.

enter image description here

This will save you having to tent the vias if it is not something you want to do - I think some fab houses can get a bit funny about doing it as well. Or at least, in my experience.

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  • \$\begingroup\$ This would be a good work-around -- using the soldermask aperture as your object rather than the via itself. Good thought \$\endgroup\$ – DerStrom8 Apr 11 '17 at 16:06
  • \$\begingroup\$ Unfortunately some board houses have relatively large minimum holes sizes for low volume prototyping tiers. I am stuck with 13.5mil vias which do not always tent well and the silk gets messy. \$\endgroup\$ – Mike Jun 1 '20 at 20:57
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The following worked for me on Altium 17:

DesignRuleUpdate

It did not work when the minimum clearance was 0 mil...likely a bug.

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If you don't want the silkscreen to touch a via, you can use the following:

Where first object matches:

OnLayer('TOP OVERLAY')

Where second object matches:

IsVIa

Then set your clearance rule.

EDIT:

I just tried this at work and to my surprise it didn't work for me either. I also tried queries such as IsDesignator, and even played around with the Silk To Soldermask rules and had no success. This seems like it may be an Altium bug. I suggest you call their customer support and see if they can give you an answer that works. Otherwise I recommend doing what I suggested in the comments, and tent your vias with soldermask. Then it won't matter if the soldermask passes over the vias or not, they should still be visible. Most manufacturers can tent vias with up to a 12 mil (0.3mm) hole diameter.

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  • \$\begingroup\$ Thank you Where will I write in this rule? Design Rules -> Manufacturing -> SilktoSilk Clearance ? \$\endgroup\$ – O.Blue Mar 29 '17 at 14:23
  • \$\begingroup\$ No, this will be a standard clearance rule: Design Rules -> Electrical -> Clearance \$\endgroup\$ – DerStrom8 Mar 29 '17 at 16:40
  • \$\begingroup\$ picresize.com/popup.html?images/rsz_20170330_091528.jpg it is not working with this settings \$\endgroup\$ – O.Blue Mar 30 '17 at 8:49
  • \$\begingroup\$ That link isn't working for me. Could you try postimage.io ? \$\endgroup\$ – DerStrom8 Mar 30 '17 at 10:18
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    \$\begingroup\$ The other thing is if you tent your vias, it won't matter if there's silkscreen over the via or not (assuming a reasonably sized via). I always tent my vias and never worry about silkscreen over them \$\endgroup\$ – DerStrom8 Mar 30 '17 at 10:28

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