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I'm designing an MCU card for a 64-pin dsPIC, something like this:

Mikroelektronika MCU card

I have several questions regarding MCU card design (two-layer board):

  1. Is it enough to place only one bulk 10uF/6.3V capacitor (tantalum), instead of 4 of them? These little buggers are quite expensive, and I've read somewhere that it is perfectly fine to use only one. I also plan to put a tactile switch on MCLR (reset) pin, and a LED indicator for power supply - both of these components would go in separate corners, leaving no space left for bulk capacitors.

  2. Is it OK to place traces under a crystal? When it comes to crystal soldering, should I leave some space between the bottom of the crystal and the board (let's say 1-2 mm), or this does not matter?

  3. The dsPIC has power supply pins on all 4 sides. Is it ok to connect these pins under the microcontroller? Something like this:

My connection

  1. I plan to use a combination of 100nF/1uF ceramic capacitors between Vdd and Vss, placed on a bottom layer. Is it enough to use only one pair, or should I use 4 pairs of capacitors - one pair for each Vdd/Vss pair? If it is OK to connect Vdd and Vss under the microcontroller (see Q3), I suppose that it is OK to use only one pair of capacitors.
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Is it enough to place only one bulk 10uF/6.3V capacitor (tantalum), instead of 4 of them? These little buggers are quite expensive

Depends on the current needs of the chip, but you don't have to use tantalum... You can use 10µF ceramic, or aluminium electrolytic, thru-hole or SMD, although they will be taller than tantalums, so that may be an issue.

Is it OK to place traces under a crystal?

It's... meeehhhh....

If you are short on space, why not use a SMD crystal instead?

The dsPIC has power supply pins on all 4 sides. Is it ok to connect these pins under the microcontroller?

GND goes to your ground plane.

You can use traces for VCC, it is wise to put a decoupling cap on each power pin. They can be under the board.

I plan to use a combination of 100nF/1uF ceramic capacitors between Vdd and Vss, placed on a bottom layer. Is it enough to use only one pai

Is this a personal project? If so, you aren't trying to save 10 cents. Put 1µF MLCC on each power pin and forget about the 100nF. ESL of 0805 caps varies very little with capacitance, so 100nF would only be interesting if it allowed a much smaller package, which doesn't matter anyway since the ESL of your chip's pins is high. So, just stick a 1µF cap on each pin...

Check the stability of your LDO with the chosen caps.

And... Add a few GND pins on each connector. Like 4 per side at least. This should keep your module from becoming an antenna if you mount it mezzanine on another board.

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I designed an almost identical board a number of years ago. There's a number of things I really don't like with that old design (such as the crystal traces) so please don't critique it.

I had a 100nF capacitor on each Vdd pin plus one single 10µF for the whole chip (plus of course one for Vcap). All my capacitors were directly under the chip on the reverse side, and I used all MLCC, although the footprints I chose for the 10µF capacitors would accommodate a tantalum if wanted.

enter image description here enter image description here

As you can see the power traces just go straight under the chip to then pass through direct to the 100nF capacitors. Those capacitors are then fed direct from the 10µF reservoir capacitor.

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  • \$\begingroup\$ Close decoupling under chip looks best in this design but ground/supply ripple margin can be improved further with isolated tracks paths to each side of chip for Vcc,Vee (star ground 4 sides of chip) Even when everything works, margin is unknown unless tested at low voltage or worst case loads with 48MHz clock. Probably ok for function but EMI not sure. \$\endgroup\$ – Sunnyskyguy EE75 Mar 30 '17 at 15:29
  • \$\begingroup\$ Vdd, Vss you mean -- it's CMOS, not TTL :P \$\endgroup\$ – Majenko Mar 30 '17 at 17:08
  • \$\begingroup\$ But yeah, the grounding is one of the things I am not happy with. These days I have it so the pad under the chip is directly connected to the ground pins to form a local low impedance ground - plus I usually use QFN when possible, and that has an exposed ground pad underneath the chip too. I can't believe that was 4 years ago now that I made that board... I still occasionally get people asking if I still make them - maybe I should take the time to create a revised version... \$\endgroup\$ – Majenko Mar 30 '17 at 17:11
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Unless you know the spike current load and ripple voltage for each side of the chip, remote response time and local decoupling response time, why guess?

It depends if 48MHz clk and bus drive sync current spikes.

They suggest 10uF <5 Ohm ESR on each side.

Quick search I found two not too expensive ? For ESR * C = 20us storage time constant ( actually 10% of this for 6% sag)

  • TPSA106M006R1500 $0.30 cut tape 500opc
  • TPSA106K006R1500 $0.1128 2k reel

yes add small C's for lower ESR underside

Xtal ... depends on accuracy you need, phase noise.

  • 3 lead holder may cause shorts if flush to board, also flush on TH XTAL not advised for lead stress to Xtal unless OK by MFG. Use a soft shim spacer.

They also sell the shims. enter image description here

Also don't cut XTAL leads with snap cuts, use shear cuts, as mechanical shock waves can stress Xtal and would be rejected by NASA stds, so take heed also 350°C max. for 3 sec. max for hand solder.

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  • \$\begingroup\$ Great info about the preference for shear cutting of xtal leads. I never knew that. \$\endgroup\$ – Wossname Mar 30 '17 at 10:43
  • \$\begingroup\$ I remember my 1st job in Aerospace, a Jr eng colleague was testing another engineers design in Tenney oven for a GOES transmitter and thermocouples were taped to unit and door, when door opened unit was pulled out and fell ~8" to hard benchtop. NASA Eng calculated shock levels to be ~500g and rejected unit so it had to be rebuilt, even tho no apparent damage. (1975) Same idea with Xtals lead cuts. (Mfg just say do not drop parts and avoid shock) \$\endgroup\$ – Sunnyskyguy EE75 Mar 30 '17 at 15:19
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(two-layer board)

Just 2 layers for a 64 pin 0,5mm pitch QFP isn't a brilliant idea. Hard to route signals and much harder to get a decent ground layout. It can be done, but consider 4 layers for a professional layout.

Is it enough to place only one bulk 10uF/6.3V capacitor (tantalum), instead of 4 of them?

You should consult the MCU manual regarding capacitance value recommendations. Usually it is around 100nF rather than 10uF. You should have a single 10uF on the supply input though. You don't have to use tantalum, use ceramic SMD caps.

The recommendation is to have one decoupling cap per supply pin. So if you have 4 supply pins, you should have 4 decoupling caps. Obviously the decoupling caps should be as close to the supply pins as possible or there's indeed no point in having several of them. The layout for the caps on that picture is horrible.

Is it OK to place traces under a crystal?

I would avoid that. Also place the crystal as close to the pins as possible. Why aren't you using a SMD crystal? Also, HC49 isn't necessarily the cheapest package any longer, there might be smaller packages that cost the same but take less space.

Depending on oscillator type, you're going to want to have some other passives there too.

The dsPIC has power supply pins on all 4 sides. Is it ok to connect these pins under the microcontroller?

Probably, it is more important to keep the grounds separate. You should at least keep analog and digital grounds separated. Overall, ground layout will be the most imporant here. If you have 4 layers with a separate ground layer, that will be ideal.

Generally, check special pins: PLL filters, ADC pins, programming interface pins etc. In particular, the reset pin. Is there a need for an external pull-up there? And it is going to need a cap too, check if the manual has a recommendation (otherwise keep it small, 100pF).

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  • \$\begingroup\$ Thank you for such a detailed explanation. Unfortunately, 4-layer boards are not an option at the moment. My first MCU card design had 4 10u (tantalum) capacitors and 4 100n (MLCC) capacitors. I now plan to have 1 10u (tantalum) capacitor, 4 100n (MLCC) capacitors - one for each Vdd-Vss pair of pins, but I've also planned to put a one 1u (MLCC) capacitor in parallel to each 100n capacitor. Is this 1u capacitor necessary? I keep digital and analog grounds separate, but I connect the three ground pins together. I'll post my design of an MCU card. \$\endgroup\$ – Marko Gulin Mar 30 '17 at 15:52
  • \$\begingroup\$ @MarkoGulin There's always this rather subjective debate about whether you should have pairs of caps with different values or not. See electronics.stackexchange.com/questions/96574/…. I would say it depends on what you are trying to filter. If you expect your supply to be noisy (50Hz?) or if you fear transients, it might make perfect sense to use larger caps. If you expect to pick up EMI from radio signals etc, then pick caps suitable to filter that frequency. And so on. \$\endgroup\$ – Lundin Mar 31 '17 at 6:42
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Theory says - not okay.
And practically, if your board is for experiments & learning, it's okay to have tracks that way.
But, my life theory says, why settle for a compromise? Work hard and make your way out, don't have tracks underneath the IC.

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  • \$\begingroup\$ If stray capacitance is 1pF at 48Mhz the Xtal coupling of harmonics will be around 1kOhm, so it depends on signals. \$\endgroup\$ – Sunnyskyguy EE75 Mar 30 '17 at 15:24

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