0
\$\begingroup\$

I'm working on implementing cordic algorithm using structural verilog description and running it on FPGAs. I want to know a way to implement D-flipflops using structural descripton. Is there a pre-defined name that would implement a DFF just like and,or,nand gates?

\$\endgroup\$
1
\$\begingroup\$

Flip-flops and latches are usually implied in HDL synthesis from a behavioural description where a value needs to be stored either between clock edges (flip-flop) or dependant on some other value (latches). It is not really necessary to make them explicit.

If you are using modules to describe basic gates for a structural description these will be vendor specific and you will need to look at the documentation from you vendor to determine the correct names. There are many types of D-type flip-flops all of which might have a different name.

If it was me I wouldn't try and implement something like the CORDIC algorithm directly with a gate level structural description. I use a behavioural description appropriate for the synthesis tools to do most of the gate level work (such as implying registers) for you.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.