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From my reading I understand that modern synthesis tools are able to perform register retiming where registers are moved between combinational logic to meet timing constraints.

So for example in your HDL you would describe comb -> reg1 -> reg2 -> reg3 and the tools would move those registers to get comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3.

When would one manually pipeline logic rather than depending on register retiming?

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3 Answers 3

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Well there are at least two scenarios where I would opt for manual retiming:

  1. Where I know there is a specific optimal geometry, for example, a logic tree, and I don't want the synthesizer to do this alone since it could make a suboptimal election.

  2. Synthesis running times can be long. I may prefer to make these decisions alone instead of letting the tool take them, where I may have to check what it did and possibly rerun synthesis.

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  • \$\begingroup\$ These are both good points, I presume that register retiming decisions are NP-complete and therefore the algorithms don't attempt to find an optimal solution but a good solution. \$\endgroup\$
    – dave
    Apr 1, 2017 at 1:30
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For RTL modules that are primarily control logic (e.g. DMA controller), manual register implementation is the best choice. For RTL modules that are primarily datapath logic (e.g. filter), synth-tool reg retiming is the best choice.

For both, in my experience, the reason is for fewer bugs and ease of debug. Determining the root cause of failure in an HDL simulation of datapath logic implemented for reg retiming (no regs mid-filter) is much easier when the result of the combinational computation/algorithm logic has no regs between its input and output. For control logic, which is largely dependent on cycle-to-cycle updates to variables (regs), the converse is true.

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Pipelining is usually done to reduce the critical path(path that has the longest delay and which determines the maximum operating frequency) of the circuit and also to increase the throughput of the design.

So while designing the RTL, we must have an idea(roughly if not exact) about which paths of the circuit are going to take longer delays. Based on this we place some registers or some other storage elements at appropriate places(within the combinational part) so as to reduce this critical path. During synthesis, the tool will optimize the positions of the registers based on the actual delay values of the gates without disturbing the functionality of the circuit.

The number of registers you place determines the number of pipelined stages in your circuit.So initially decide on a certain number of stages and synthesize it to check whether the design has met the specifications.If the design hasn't met the timing and you want a faster circuit irrespective of power and area consumption then increase the number of pipeline stages.

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  • \$\begingroup\$ This answers why I would add registers. In my example three stages has been determined to be sufficient. But why would I split the combniatoric logic versus using register retiming to achieve the end goal. \$\endgroup\$
    – dave
    Apr 1, 2017 at 1:28

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