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This is what my clearance rule looks like: enter image description here

My grid distance looks like this: enter image description here

And the final result, after DRC, looks like this:

enter image description here

As you can see, although not by a very large margin, the distance is clearly larger than 0.15, specified in my DRC rule set. This is not the best example, as I just clicked the error list randomly and this showed up.

What did I do wrong? How do I tackle this?

Thank you for your help! Edit: this might be the problem:

enter image description here

These are all "stock" packages from the lbr came with eagle, anything I can do or I just have to click through everything?

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  • \$\begingroup\$ Does Eagle check the distance between the soldermask openings around pads? That may be your issue. \$\endgroup\$ – DerStrom8 Mar 31 '17 at 10:33
  • \$\begingroup\$ While sounding like a complete idiot, where can I disable/modify this "check soldermask openings" function? \$\endgroup\$ – Matt Cox Mar 31 '17 at 10:35
  • \$\begingroup\$ You're not sounding like an idiot, don't worry. I honestly can't remember if Eagle even does such a check. I haven't used Eagle in about five years. \$\endgroup\$ – DerStrom8 Mar 31 '17 at 10:41
  • \$\begingroup\$ Well lucky you! I just picked it up after 10 years of never heard of it. It's a mess. Anyway, I enabled all layers, seems the only layer that may violate the rule is tStop and bStop. Can I do something about it or I just have to do it the hard way? \$\endgroup\$ – Matt Cox Mar 31 '17 at 10:46
  • \$\begingroup\$ Yep, tStop and bStop are the soldermask layers, so that seems to confirm my suspicion. Where did you get the footprint? Really the only thing you can do is edit the pads and reduce the soldermask expansion, or separate the pads more. \$\endgroup\$ – DerStrom8 Mar 31 '17 at 10:51
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It's not clear exactly what's going on, but check your net classes. The stuff in the DRC settings are minimums. More conservative settings elsewhere can override them.

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  • \$\begingroup\$ Hello Onin, making an uneducated guess, the problem is with tStop and bStop layer, can I override that? I'll see if I can upload a image to make it more clear, please refer to the edited question. \$\endgroup\$ – Matt Cox Apr 1 '17 at 1:42
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While I didn't have a thorough look at your clearance rules in Eagle, I noticed that you mentioned "stock packages" in your design. Be very careful when using these standard packages contained in the Eagle "stock" libraries. I have been the victim of using a standard MCU package in the Eagle library, only to realize much later (after PCB manufacturing!) that the pin layout of the MCU in Eagle was completely different than the actual pin layout of the real component. I had to edit the existing component and copied into my own personal components library.

Eagle's libraries are very useful to get started with your PCB designs, but you will reach a point where you will have more peace of mind in creating your own components for use in your designs, or at the very least edit existing packages in the Eagle libraries to be absolutely sure that use trustworthy packages in your designs.

I can strongly recommend that you create you own component library of the components that you use most often. With Eagle's vast array of components in its libraries, it is very easy to mistake one component for another, where there might be slight differences not so easily picked up by the average eye.

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