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So while analysing the waveforms, I have noticed spikes in the ouput during input transitions for gates like inverter, nand etc. and so I was asked to look up Miller effect to explain the phenomenon. After reading through the topic (how Cgd appears across the input and the output) I found that this is caused due to the capacitive coupling of the input to the output by the gate drain capacitance. I can neither grasp the theory behind this completely nor can I figure out how the spike decays back to the supply voltage after a few moments. Can someone give me a detailed explaination for this effect. PS. this is what the waveform looks almost like except that the spikes appear when output switches to one and when it switches to 0 (opposite to the waveform) like: enter image description here

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    \$\begingroup\$ How about a circuit diagram? \$\endgroup\$
    – Andy aka
    Mar 31 '17 at 14:00
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    \$\begingroup\$ These kinds of spikes often indicate inadequate or too-far-away supply bypass capacitors rather than a Cgd issue. \$\endgroup\$
    – glen_geek
    Mar 31 '17 at 14:03
  • \$\begingroup\$ you mean leading-edge overshoot in both polarities with a bridge driver or CMOS output? load Impedance mismatch with inductance \$\endgroup\$ Mar 31 '17 at 14:09
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In order to change the voltage across a capacitor, you need current:

\$i_C=C\frac{dv_C}{dt}\$

The capacitor \$C_{gd}\$ connects input to output. So if the input were to change instantaneously from 0V to VDD, the voltage over \$C_{gd}\$ would have to change from VDD (\$v_{out}=VDD, v_{in}=0V\$) to -VDD (\$v_{out}=0V, v_{in}=VDD\$) instantaneously. This could only happen if an infinite amount of current flows through the capacitor!

As the input suddenly rose from 0V to VDD, the NMOS transistor switched on, and the PMOS transistor switched off. As you may know, the NMOS transistor will be in saturation, and will sink a pretty constant current to ground. This current is far from infinite! And so the capacitor can only slowly decrease its voltage. Instantaneously, it should retain all its charges as it hasn't had time to lose them through the NMOS. So at the exact instance where the input switches, the output will have to follow by the same amount of voltage.

Instantaneously, output will jump up from \$VDD\$ to \$2\cdot VDD\$... if no other capacitances are present.

If there are capacitors connected to the output, then they will not like the output to be changed instantaneously because it would mean they need an infinite current as well. So \$C_{gd}\$ will have to "fight" over the output voltage with all other capacitances connected to the output (actually, the charges stored on the capacitances are redistributed, this redistribution of charges will result in an infinite instantaneous current).

The output voltage they will agree on will depend on the capacitance of those capacitors. In the end, this causes the output not to jump over the full \$VDD\$, but some smaller voltage.

You will see that if you increase the capacitance at the output, that the peaking will get smaller and smaller. Unfortunately, the slew rate at the output will also get smaller and smaller...

The following figure summarizes everything into one image. \$C_L\$ is the total load capacitance, which is the sum of all capacitances connected to a constant voltage.

Stages of pulsed invertor (ideal input)

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  • \$\begingroup\$ This is by far the simple and best explanation I have got for this phenomenon. Thank you. \$\endgroup\$
    – Adithya
    Jun 4 '18 at 5:56
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Examine this schematic of a CMOS inverter:

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ The values of C1 and C2 that you have used in the schematic is giving me a large delay so I brought them down in femtos . Even then I don't understand the way the input is coupled to the output for such a small period. For the positive spike a part of the input is added to the output waveform but how is it that the output falls below zero during the other transisition. \$\endgroup\$
    – Adithya
    Apr 1 '17 at 10:26
  • \$\begingroup\$ Suppose the FETs have 100uA drive strength. Lets compute the C_gate_drain_overlap charge injection. Assume 0.1pF Cgd overlap, with 10 picosecond edge for 2 volts. What is the current? Q = CV, I = C * dV/dT, and if I is greater than 100uA, the input has over-driven the output. Now lets compute the current flowing through the 0.1pF. I = CdV/dT = 1e-13F * 200 Billion volts/second = 1e-13 * 2e+10 = 2mA. The displacement current through the Cmiller is 20X stronger than the Inverter output FETs. \$\endgroup\$ Apr 2 '17 at 2:08
  • \$\begingroup\$ Thanks a lot, it makes a lot of sense now. What you mean to say is that the 10ps transition of the input waveform is causing a comparatively higher drain current to charge the load capacitance, which results in the spike and when the input has stabilised to vdd after 10ps the current resulting due to Cgd is insignificant and so the spike dissapears. So Cgd plays a role only during the transition and can be ignored pretty much anywhere else? \$\endgroup\$
    – Adithya
    Apr 3 '17 at 7:39

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