I'm trying to come up with a way to do overcurrent protection for the following circuit: schematic My first thought here was to monitor the increase in voltage drop over one of the mosfets (M1) and via a zener (D5) (that sets the cutoff level) activate a transistor that drains the gate. The zener is a 1.8V one and combined with the 1 voltage drop of D4 i thought it would cutoff at 2.8V which would be 3-4A for a irf740. But it's not cutting off anything.. any thoughts on how this function could be implemented into this circuit?

  • \$\begingroup\$ Shouldn't you reverse D4? \$\endgroup\$
    – peter
    Mar 31, 2017 at 21:47
  • \$\begingroup\$ Look carefully at what happens with Q3 when both MOSFETS are OFF. Do you see that you could never turn the MOSFETs on? \$\endgroup\$ Apr 1, 2017 at 5:30
  • \$\begingroup\$ I assume R3 is not really 1K ? \$\endgroup\$
    – Russell McMahon
    Apr 1, 2017 at 7:01
  • \$\begingroup\$ Thanks for the input! Indeed my current circuit seems lite a horrible attempt :) Any thoughts on how a overcurrent protection using the voltage over the mosfets could be implemented? \$\endgroup\$
    – englund
    Apr 1, 2017 at 11:34
  • \$\begingroup\$ Rds_on of a FET does give you a convenient way to crudely estimate current by measuring the voltage across it, but of course it only works while the FET is solidly on! While it's off or transitioning, such an overcurrent detector would panic unless it was blocked or disabled somehow. \$\endgroup\$
    – AaronD
    Jun 29, 2017 at 5:41

2 Answers 2


After much thought about this circuit.

First concentrate on the dynamic switching times of the two IRF740. Their switching on/off times are under 50nSec. Operational failure modes of most all AC switching supplies is transient damage.

That said do not couple the gate control direct to the AC connections. The time constant of your current limit circuit is way to slow. Go back and think of a simple LC current lag network. It could trigger an off state for U1 for example.

  • \$\begingroup\$ Hmm, but wouldn't disabling U1 be even slower than directly draining the gate? \$\endgroup\$
    – englund
    Apr 1, 2017 at 11:36

You could use something like a positive peak detector (simple RC circuit) to monitor the voltage across the switch and compare it to a fixed reference. Fixed reference can be formed using a simple voltage divider.

However, since the circuit is a 50Hz sinusoidal AC, two monitoring circuits would be necessary. (To protect over current in both positive and negative cycles) Probably try to OR the voltage later on. enter image description here

This circuit might need some blanking time initially (I'm talking about the case where voltage across the switch goes from the peak to normal saturation voltage).


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