# Why can't regs be assigned to multiple always blocks in synthesizable Verilog?

The accepted answer to this question notes that "every reg variable can only be assigned to in at most one always statement". It's clear that in a lot of cases assigning a reg to multiple always blocks is meaningless. However, it's seems that there could be hardware-meaning instances of a reg in different always blocks.

For example, what if a same reg is assigned to always @(posedge clk1), always @(posedge clk2) where clk1, clk2 never beat of the same time? There would be no race-condition.

Why is there a "hard rule" concerning regs in different always blocks?

The case you mention will not be synthesizable. The flip-flop that implements the reg can only be clocked from one source.
As an aside, I'd like to clarify that the rule about regs having affinity to always blocks affects synthesizability, not validity. Software simulator will handle assignments from different always blocks without any problems.
• DDR flip-flops (available in IO blocks of many FPGAs) react to both edges. But even then, there's only one input, so it doesn't make sense to have the logic split up into multiple blocks. always @(posedge clk or negedge clk) or just always @clk would make sense. Even so, I'm not sure if any tools will synthesize those -- I have always explicitly instantiated the library block instead. Apr 10, 2012 at 15:36