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The design I am working on has about 30 capacitive buttons, LEDs for back-lighting, about 8-10 ICs (capsense controllers, LED drivers, MCU, etc), many passive components and coin cell batteries.
I am using Cypress MBR3 Capsense controllers for this application. Board size is such that the whole top layer is covered with capacitive buttons. Buttons pitch is 20mm.

I have two questions:

  1. PCB stackup
    I asked this question on Cypress forums as well and got this recommendation.

    4-Layer PCB:

    • Place the sensors on the top layer of the PCB.
    • Route the sensor traces in the layer-2.
    • Place a hatch fill of 7-mil trace and 70-mil spacing and connect it to ground in layer-3.
    • Place components in the bottom layer, The unoccupied areas can be filled with a hatch copper fill of 7-mil trace and 70-mil spacing and should be connected to ground.

The problem with this stackup is that I only get one layer for components and digital traces but I need at least two layers for digital signals.

So should I choose a six layer stackup? If yes, what should be the copper, prepreg and core configuration?

Can I make layer-3 and layer-4 Power planes in a six layer stackup? For normal six-layer PCBs, usually layer-2 and layer-5 are power planes but here I need sensor traces on layer-2. One other requirement for capacitive sensor PCBs is that the spacing between sensor traces (layer-2) and ground plane (layer-3) should be larger to minimize parasitic capacitance.

  1. SMD LEDs on top layer
    Most common recommendation for back-lighting in such applications is to drill a hole at the center of button electrode and place back-firing LEDs at the bottom. But since I have a lot of components to place, I can't have a 2-3mm hole every 20mm.

So can I place surface mount LEDs (say, 0603) on top layer at the centers of electrodes?
I have never seen such example in manufacturers' layout guidelines.

Edit:

Can I go with this odd 5-layer stack-up? It satisfies the CapSense recommendations and gives me two layers for digital signals :)

5 Layer stack-up screenshot

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    \$\begingroup\$ 6 layer board is expensive but may be needed to overcome bad surface area planning of size of 2 to 4 layer design. The finger / sensor+tracks capacitance ratio is critical like Signal to Noise Ratio. You ought to review other designs that use this chip and repeat thru all the design guides. Budget, finger SNR, EMI and wet surface contamination effects must be defined before design starts otherwise expect failure unless you copy good design that you know meets all specs. small scale test & measure is good idea for different designs until you gain proper experience. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Apr 1 '17 at 13:22
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    \$\begingroup\$ You must master the understanding of differential capacitance and EMI control to make this inexpensive. Active Guarding reduces capacitance but also more EMI if done wrong. with 30 to 50MHz button signals unless you create random sine sweep ( not square wave) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Apr 1 '17 at 13:36
  • \$\begingroup\$ @TonyStewart.EEsince'75 The design examples I have found from design guides are mostly for 2-layer PCBs and a few for 4-layers. I am unable to find any example for 6-layer and if I follow the recommended layout guidelines, I get only one signal layer. That's why I am seeking advice from more experienced designers. \$\endgroup\$ – Shihab Apr 3 '17 at 0:21
  • \$\begingroup\$ Coin cells driving LEDs will result is very short operating time. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Aug 13 '17 at 12:33
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The amount of layers shouldnt matter, as long as you carefully control the capacitance seen by the buttons. If you can control the capacitance from the top layer sensor pads and their traces, to the nearest reference plane, then you should be safe to do whatever you want bellow that plane if i am not mistaken (keep in mind, this recommendation is not based on experience!) as the capacitive coupling will be primarily to the first reference plane.

You also need to be very mindful that the buttons and their traces are a EMC hazard and they are sensitive to parasitic coupling. All your digital stuff has the potential to send you back to the drawing board when your board fails EMC testing due to coupling into the sensor pads.

I have done a 4 layer capacitive design before, but no extra electronics except level translation, I2C and some LEDs. But i remember the LEDs toggling on and off shifting the measurement levels of the sensors visibly, so sensitive were they to EMI.

If i was going for a 6 layer stackup. I would consider this one (up for scrutiny here).

-Sensor pads + traces

-Reference Ground (Sensor ground)

-Power

-Signal

-Ground

-Signal

The reasoning is that the first two layers establish the pad capacitance, the next power layer provides isolation of digital signals against the sensor pads by holding any digital return currents that might otherwise flow on the sensor ground. This stackup also fullfills having reference planes close to any digital signal layers. This is what i would personally start with.

The main issue with adding layers is that the average distance between them gets smaller and smaller, you might need to design the layer stackup to really sqeeze the inner layers together, to get the needed separation between the sensor ground and the pads, while still maintaining a symmetric stackup as asymmetric ones are really really unpopular for many reasons.

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  • \$\begingroup\$ sorry for late response. That's an excellent stackup recommendation for my requirements. Maybe, instead of having a much thicker prepreg/core between layer 3 & 4, I can have thicker prepreg between layer 1 & 2 and layer 5 & 6 while squeezing inner layers together \$\endgroup\$ – Shihab Apr 16 '17 at 10:15
  • \$\begingroup\$ Also, I have checked Analog Devices touch solutions. Their PCB requirements seem to be pretty relaxed. See their [Layout guidelines](www.analog.com/media/en/technical-documentation/application-notes/AN-957.pdf). It seems I can use 4-layer stackup too. But shouldn't layout requirements be same for capacitive sensing irrespective of IC manufacturer? what do you think? \$\endgroup\$ – Shihab Apr 16 '17 at 10:22

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