The design I am working on has about 30 capacitive buttons, LEDs for back-lighting, about 8-10 ICs (capsense controllers, LED drivers, MCU, etc), many passive components and coin cell batteries.
I am using Cypress MBR3 Capsense controllers for this application. Board size is such that the whole top layer is covered with capacitive buttons. Buttons pitch is 20mm.
I have two questions:
- PCB stackup
I asked this question on Cypress forums as well and got this recommendation.
- Place the sensors on the top layer of the PCB.
- Route the sensor traces in the layer-2.
- Place a hatch fill of 7-mil trace and 70-mil spacing and connect it to ground in layer-3.
- Place components in the bottom layer, The unoccupied areas can be filled with a hatch copper fill of 7-mil trace and 70-mil spacing and should be connected to ground.
The problem with this stackup is that I only get one layer for components and digital traces but I need at least two layers for digital signals.
So should I choose a six layer stackup? If yes, what should be the copper, prepreg and core configuration?
Can I make layer-3 and layer-4 Power planes in a six layer stackup? For normal six-layer PCBs, usually layer-2 and layer-5 are power planes but here I need sensor traces on layer-2. One other requirement for capacitive sensor PCBs is that the spacing between sensor traces (layer-2) and ground plane (layer-3) should be larger to minimize parasitic capacitance.
- SMD LEDs on top layer
Most common recommendation for back-lighting in such applications is to drill a hole at the center of button electrode and place back-firing LEDs at the bottom. But since I have a lot of components to place, I can't have a 2-3mm hole every 20mm.
So can I place surface mount LEDs (say, 0603) on top layer at the centers of electrodes?
I have never seen such example in manufacturers' layout guidelines.
Can I go with this odd 5-layer stack-up? It satisfies the CapSense recommendations and gives me two layers for digital signals :)