please refer to the image below for the overall idea: enter image description here

In eagle, there is a layer called "tStop" and with its counterpart for bottom layer being "bStop". As I manage to gather, it's some sort of mask that stops the green insulation so it won't cover up your pads, vias etc.

Now as you can see in the picture, two tStop masks overlapped, which logically speaking shouldn't be a problem since it means during board fabrication, this area will not be covered by insulation, the overlap at worst and at best, serves as some sort of double guarantee.

But the problem is that eagle list this as an error, which doesn't really impact my board in any significantly negative way. And I now have close to a thousand of errors mixed with actual problematic ones, which makes it quite difficult to ignore/approve by hand, so, what I am asking is, can I disable/overwrite it? Hide these error of the same nature at least, while leaving the rest shown?

The errors look like this with no details listed and no hint to work with: enter image description here

  • \$\begingroup\$ Are you sure that this is actually about the mask, and it's not warning you about copper clearances? \$\endgroup\$ – Abe Karplus Apr 1 '17 at 6:28
  • \$\begingroup\$ I'm fairly sure. The clearance was set to be 0.15mm, the grid, if you cared to count, was set to be 0.01mm, there are a total of 40+ grids between the 2 coppers. \$\endgroup\$ – Matt Cox Apr 1 '17 at 6:45
  • \$\begingroup\$ That's odd. I'm not able to get any clearance errors from overlapping stop masks, nor do I see any DRC option that would cause it, in 7.7. What Eagle version are you running? \$\endgroup\$ – Abe Karplus Apr 1 '17 at 8:01
  • \$\begingroup\$ Free version of Version 8.0.1. I'm not proud of myself. Maybe this is newly add fuction? \$\endgroup\$ – Matt Cox Apr 1 '17 at 8:07
  • \$\begingroup\$ @AbeKarplus Just let a friend of mine working in college tried it on 7.6.0, same result, all the tStop mask overlaps got lit up. \$\endgroup\$ – Matt Cox Apr 1 '17 at 8:12

Just made the observation after posting this answer - you need to be able to understand the errors that are being reported, it tells you what layer the errors exists on, in your case layer 1. This is the layer for top copper so you know that it is the clearance from this layer. Stop mask errors, as mentioned, will come up as "Stop Mask" and will also tell you what layer, tstop is layer 29! Continue reading full answer below for step by step on proof.

This error that you are getting is not actually to do with the stop mask. You could find this out by going to the DRC and selecting the "Masks" tab and changing the values of the Min and Max to, say, 1 mil and this will make them much smaller and no longer overlapping and thus, shouldn't be a problem for the DRC if this was the issue. See images below for proof that this is not the case.

enter image description here
enter image description here
enter image description here

I changed the stop mask parameters to 1 mil each so that they definitely weren't overlapping. I then cleared the list of current errors before running the DRC again - as you can see, the errors remain regarding the clearance.
This flag only occurs when the DRC constraints in the "Clearance" section are breached, so in other words, the copper pads are too close to each other.

See images below for proof of fix - I once again went into the DRC and went into the "Clearance" tab and changed the pad to pad parameter to 1 mil - this is just for proving the point - cleared the errors, and ran the DRC check again and the errors were removed.

enter image description here
enter image description here

You can still see "Stop Mask" errors, and this is because the component outline drawing is overlapping the stop mask - this is how stop mask errors are shown.

I am running Eagle 8.1.0 - I see your point about your grid lines, there are 29 squares diagonally between the pads so the DRC shouldn't be flagging them if what you are saying is true - check your units (mil are not the same as mm), move the pads further apart if possible, or reduce the constraint in the DRC regarding copper clearances. If your minimum clearance is set, you should keep your grid to this or greater than if possible in order to avoid circumstances such as this.

  • \$\begingroup\$ yes they are layer 1 (top copper) errors - so copper, not stop-mask - these are real errors that need to be fixed, either by moving them further apart or by choosing a process (and as a result matching design rules) that will let you put copper that close \$\endgroup\$ – Taniwha Nov 3 '17 at 5:32

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