# How can i calculate the time that is elapsed between two sensors in vhdl?

I am new to digital design and having trouble in calculating the time between two sensors that gives digital output? How can i approach to this problem? I thought of writing the outputs of digital sensors in the process statement and when the first sensor gives 1 it starts the time and when the second sensor gives 1 it stops the time. However,since the sensor i am using gives 0 right after a moving object moves infront of it i cannot store the time. Does anyone has suggestions about it? Thank you.

• It does not matter whether your signals are HI or LOW. Just implement the counter that would start with a signal 1 and stop with a signal 2. Then, you multiply counter value by the period of the clock that runs the counter and you will get time. Apr 1, 2017 at 13:34
• Hi there. It is very important that you have already understood that VHDL is not a software programming language running on a CPU but a descriptor language for creating digital circuits. VHDL is a glorified circuit diagram. So if you want to time your events, sketch out the digital circuit blocks that can do this. Afterwards, implement that circuit in VHDL. I don't know your VHDl experience but if it's basic, this will help. I imagine your circuit will filter (noise/metastability reject) your inputs then count clocks between them changing states. Have a go and edit/add this to your question. Apr 1, 2017 at 14:52
• Please correctly formulate the last part of your question Apr 4, 2017 at 17:21

This is the function of a Time-to-Digital Converter. The idea is that you start a counter when the sensor 1 gives a 1 and stop it when sensor 2 gives a 1. The precision is determined by the clock frequency of the counter. It is even possible to have higher precision if you add an interpolator (the Nutt method), but I don't think you require it.

To detect the rising edge, implement edge detectors:

    signal sensor1delay : std_logic;
signal sensor1r_edge : std_logic;
begin
sensor1delay <= sensor1 when rising_edge(clk);
sensor1r_edge <= '1' when sensor1='1' and sensor1delay='0' else '0';


edit: The Q <= D when rising_edge(CLK); construct is perfectly legal VHDL (since VHDL93), and supported by all modern synthesis software afaik. More people are using it, just Google it. It is also described in "Effective Coding with VHDL" by Ricardo Jasinski

then just count:

    signal counter : natural;
signal output : natural;
begin
clock_proc: process(clk)
begin
if rising_edge(clk) then
if sensor1r_edge='1' then
counter <= 0;
else
counter <= counter+1; -- overflow error in simulation, not in synthesis
end if;
if sensor2r_edge='1' then
output <= counter;
end if;
end if;
end process;


Your last part is unclear: what do you mean with "after a moving object moves infront of it i cannot store the time"

Edit:

It is likely also necessary to implement (clock domain) synchronizers for the sensor inputs.

• " sensor1delay <= sensor1 when rising_edge(clk)"? That's a terrible no-no but it will simulate. You have shown no input filtering or metastability rejection, which is essential. I have to ask: are you very new to VHDL? It looks like it, this is bad guidance. Apr 5, 2017 at 7:21
• @TonyM I've been programming VHDL for almost 18 years now (wow is it been that long already? I'm getting old ;) ). The construct is supported since VHDL-93. I haven't encountered a synthesis tool that doesn't support it yet. Who told you that this is bad practice? Apr 5, 2017 at 7:56
• Thanks for your reply. I've never programmed in VHDL but I've been designing digital circuitry in VHDL professionally for 19 years, for a lot of different companies into industrial, military, avionics and space equipment, in large fast FPGAs, tight gate-efficient CPLDs and ASICs. I've done new designs, redesigns and design expansions and naturally reviewed/worked on/with a lot of other people's VHDL along the way. I aim for a 'works perfectly first time', through good understanding of the system, experience and testbenches large and small, and have got close to it most times. I try :-) Apr 5, 2017 at 9:46
• And I've never seen that trick in anyone's VHDL, nor the need for it :-) What's wrong with a standard-format process? Clear, simple, easily recognisable and therefore maintainable is what's valuable in industry. Getting it through the tools is a long way from an endorsement. Mechanical drawings could use exciting different formats, just to be novel, but there will be indirect costs and errors introduced from that deviation. Pick what people recognise. C'mon, idea is make reliable equipment and profit, isn't it, not just to have fun with the language. We're not on holiday or at school here :-) Apr 5, 2017 at 9:50
• It's only recognizable if you're used to it. But why do something in six-seven lines, when you can also do it in one? Languages are evolving. VHDL-1987, 1993, (2000/2002), 2008 every time it's easier to program. Same for languages like C++: now you can write for(auto element : vector) instead of for (vector::iterator it=vector.begin(); it<vector.end(); it++). Synthesis is also becoming more powerful. You could even use wait until rising_edge(clk) (limited) in the process statement to infer a register. I worked on a lot of old code and imho maintainability is determined by readability. Apr 5, 2017 at 10:04