I have a wire to which I assign a complex right-hand-side expression with lots of bitwise operations. This right-hand-side expression is quickly becoming long and hard to maintain.

Is there a way I could replace the bitwise operations by if/else or case statements to help readability and maintability?

  • \$\begingroup\$ Can't you just define intermediate wires? Then you can also give your intermediate signals intelligible names, further improving maintainability... \$\endgroup\$
    – vicatcu
    Apr 10, 2012 at 12:22
  • 2
    \$\begingroup\$ Also, many people avoid it in C-family programming languages, but to be proficient in Verilog you must become familiar with the ternary operator ?:. \$\endgroup\$
    – The Photon
    Apr 10, 2012 at 15:31

1 Answer 1


Sure you can, just use the always @(*) construct (you need to make it a reg). You can handle inout ports easily too.

reg res;
assign inout_port = dir_out? res: 1'bz;
always @(*) begin
    if (x == 42 && y != z)
        res = 10;
        res = y * 12;
  • \$\begingroup\$ The problem is that I cannot make it a reg because it is an inout port. \$\endgroup\$
    – Randomblue
    Apr 10, 2012 at 12:20
  • \$\begingroup\$ I've edited. Note that you shouldn't be using inout ports for internal connections anyway. \$\endgroup\$
    – avakar
    Apr 10, 2012 at 12:24

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