Can anyone suggest possible reasons why this might be happening? Compilation is succesful. We have analyzed the code. Can't figure out any logical errors or syntax errors(else wouldn't compile).


closed as unclear what you're asking by duskwuff, DoxyLover, Dmitry Grigoryev, Autistic, Voltage Spike Apr 3 '17 at 15:48

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  • \$\begingroup\$ Show us your code. We aren't psychic -- we can't debug your code without looking at it. \$\endgroup\$ – duskwuff Apr 2 '17 at 17:25
  • \$\begingroup\$ Welcome to EE.SE! Your question is very minimal, can you give more information? Like duskwulf says, some code would be helpful, but not just that. What data types are you using? What FPGA? What are you observing exactly (maybe add a screenshot)? What have you tried to achieve your goal and to fix the problem? Etc. As it stands, your question runs the risk of being closed. \$\endgroup\$ – marcelm Apr 2 '17 at 17:40
  • \$\begingroup\$ As said, there's no details so help can only be minimal. Answering the question you have posted, I imagine you have a broken path or input and your design is being thrown away by the optimiser during synthesis. \$\endgroup\$ – TonyM Apr 2 '17 at 18:24
  • \$\begingroup\$ @thebionicandroid There are ways to solve this: simulate the compiled code, most synthesisers have a way to output hdl code that can be simulated in modelsim. \$\endgroup\$ – Voltage Spike Apr 3 '17 at 15:47

My bet is that you didn't attach the core IO to pins, so the optimizer went llike this:

"Hmmm... there's this whole bunch of code with constant inputs, and none of its outputs is actually used."

In this case, the optimizer... optimizes. Unused code is removed. Synthesis tools are pretty good at this, because they have to.

  • \$\begingroup\$ Yeah, we wrote code for the output module and that jumped up to 10,000 logic elements. Thanks. \$\endgroup\$ – thebionicandroid Apr 3 '17 at 8:47

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