It's a CE followed by 2 CC stages. I don't have power resistors or bjts, which is why I have 2 transistors and 4 resistors in the second CC stage.
I put 2 CC stages because I needed a lot of bias current for the output transistors, meaning R8-14 are small, but the CE input stage didn't like driving a low impedance so I put another stage in between.
The simulation works pretty well and drives the 8 ohms with ~250 mW.
My questions are: 1.) Does it make any sense to match the DC level between stages if the stages are AC coupled?
2.) What is the minimum limit for collector current? Is it just when the internal pn junctions stop being fully on?
Any other comments on the circuit are appreciated. I apologize if I didn't do enough searching before asking.
I checked the meta and it said design review questions are okay as long as they're kind of constrained.