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So I'm just getting my feet wet with CPLDs, in fact I programmed a chip successfully for the first time last night (success being programming it with the correct program, not the one recovered from it which is what I think I did the day before), and I got an output pin set to high meaning I can light an LED (with appropriate resistor).

Then I wanted to make it flash, and set about using the internal oscillator. I'm using Quartus Prime, and found the oscillator and tied it to an input pin that I left unassigned for the OSCENA, thinking that would default high. I fed that as the clock into a 74xx counter and used the high bit to drive the LED, but no joy.

how do I ensure a wire is high in the schematic builder?

From research this seems to be quite easy using Verilog or VHDL and found examples, but I am a software developer so doing so holds less interest for me as for such a simple use case it boils down to something akin to a for loop.

This is what I've cooked up so far, using the guide available here to make the oscillator available:

Schematic showing the Max II oscillator hooked up to an input switch and output LED

The guide says "make a wire, give it a logic value of 1" and that doesn't seem possible here, though I checked the Verilog provided and it seems they're basically hooking up a switch, so I did the same.

From what I understand the 7457 is 1:60 frequency divider, and I know that even dividing this oscillator's clock by 60 isn't going to help on the human scale, I thought I'd see something when running a simulation, but that seems to not be the case.

Simulation setup:

Setup of Quartus simulation

And the result, showing the clock output as "unknown" (too fast?!) and the LED as logic low.

Simulation results

So, any pointers on what I'm doing wrong?

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    \$\begingroup\$ I do electronics/VHDL design and software so I don't understand why it's apparent that it'd hold "far less interest" for you. Writing software is very different from designing digital logic in VHDL/Verilog (not recognising that distinction produced some of the worst VHDL I've seen professionally). Any road up, you need to post a lot more than you have for anyone to see how far you've progressed, let alone offer suggestions - this is just a sketchy summary. \$\endgroup\$ – TonyM Apr 4 '17 at 7:47
  • \$\begingroup\$ Sorry for that, bad wording I guess... it's just the examples for this super limited use case were pretty much define some variables and write a for loop :) I'll play around some more and show what I've done. \$\endgroup\$ – Matt Lacey Apr 4 '17 at 10:49
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    \$\begingroup\$ No harm done :-) Important point on VHDL, though. There is no CPU, only a dedicated logic circuit that you're designing. The 'designing' - not coding, not writing - separation in one's head is paramount to getting the very best out of it. So it's: design a reload-on-zero down-counter circuit, implement that circuit in VHDL, write a testbench and try that out on the simulator (free ModelSim?). Then, when you're sure it works, only then synthesise it and try out something you expect to work. Problems are found on the simulator, not on the equipment :-) You probably know half of this anyway. \$\endgroup\$ – TonyM Apr 4 '17 at 11:06
  • \$\begingroup\$ @TonyM Expanded a little... any pointers at all would be a huge help! \$\endgroup\$ – Matt Lacey Apr 5 '17 at 13:10
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    \$\begingroup\$ Maybe the reset pin has to be held low. There are 'vcc' and 'gnd' elements under primitives. Schematic design for PLDs/FPGAs is really not a good idea, as much as I like it. \$\endgroup\$ – τεκ Apr 7 '17 at 16:09
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The Oscillator

So the truncated "clock:" line in my second image in the question was for the output of the oscillator. Turns out that when it's forced unknown (the hatching) it stays that way, though if you hook it up to an output then that output changes as expected:

enter image description here

enter image description here

The LED Output

The reason the LED output in the original wasn't working was that I'd not hooked it up correctly. As (τεκ)[https://electronics.stackexchange.com/users/6127/%cf%84%ce%b5%ce%ba] pointed out, the divider's reset needed to be held low for it to work, and because I hadn't read the datasheet and made an assumption, I hadn't realised that CLKA only drives QA, CLKB on the other hand drives QB and QC, with QC being half a 2:1 reduction of the former. So this circuit:

enter image description here

Produces a much more satisfying (albeit still super fast) output which has a 60:1 reduction:

enter image description here

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