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I'm reading a history of EDA for ASICs because I'm curious about how older ICs were mass-produced.

The article explicitly mentions that in the early 1970's, SPICE was used to simulate circuit behavior, and cut rubylith was laid out to ensure that the ASIC design matched the schematic correctly (layout versus schematic):

What we now know as physical design verification consisted of taking flatbed plots of the layouts, pinning them on the wall or laying them on a light table, and having people try to find errors. Hence, physical verification was one of the first businesses to be adopted in the emerging custom design space (see "The More Things Change, The More They Stay The Same,").

However, the article doesn't really go into how designers ensured that ASIC features such as gates, would work correctly when the layout was shrunk to create a mask. Assuming an ASIC mask mistake was comparatively expensive in the past as it is today, what techniques were used to minimize the risk of a defective mask due to improper physical dimensions of features, such as a gate?

Considering geometry is important for an ASIC, were predictions of field strength using Maxwell's equations typically used (analogous to a 2.5D field solver for PCBs today), or were simple transistor models based on length and width sufficient? Or were physical dimension tolerances sufficiently large as to not be a significant source of error during manual layout?

To reduce the scope of the question, let's assume digital ASICs of the era such as TTL or 6502.

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  • \$\begingroup\$ I remember the large tape outs and light tables. Mask dimensions were large then and so the mask image very closely looked similar to the tape out. Some diffraction. But only a little. These days, a mask may look very little like the intended result seen under an electron microscope and special processing is absolutely required. Or are you asking something different and I misunderstand? \$\endgroup\$ – jonk Apr 5 '17 at 7:30
  • \$\begingroup\$ @jonk I'm asking how important was analyzing the physical dimensions of the rubylith's (or tape out's) features, such as gate and transistors, to predict whether the final IC would function properly. \$\endgroup\$ – cr1901 Apr 5 '17 at 7:36
  • \$\begingroup\$ In the earlier days when the whole thing was done by cutting rubylith getting and measuring the right dimensions was critical, but the devices were very simple. In the early days of CAD the cells were put down as cells in cookie cutter form and by that stage we were able to assume that the computer generated geometries within a cell and for connectivity were correct. \$\endgroup\$ – RoyC Apr 5 '17 at 7:57
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Too give the best chance of a device working as expected in an asic cell library we used to work in a system of increasing abstraction.

The spice models for the technology would be written based on mos transistor theory and verified against a test chip which contained a few devices. The Transistor theory always seemed to be fairly accurate but we were not dealing with sub micron technology with a bunch of secondary effects at the time.

This spice model would be used to develop the rest of the cells in the library. These cells would be put on a test chip. This would be manufactured out at the "corners" of the technology. This involves deliberately introducing manufacturing variation (doping,geometry etc) to give fastest and slowest cases. The test chip would be evaluated to produce the digital simulator models which would be used for individual device design.

I don't go back to the days of rubylith but I can remember doing manual checks of cell connectivity on coloured transparent prints (one per layer) before computer CVS (connectivity verification by computer). Took a few days for a 3k gate asic.

In the earlier days when the whole thing was done by cutting rubylith getting and measuring the right dimensions was critical, but the devices were very simple. In the early days of CAD the cells were put down as cells in cookie cutter form and by that stage we were able to assume that the computer generated geometries within a cell and for connectivity were correct.

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  • \$\begingroup\$ All answers are good/got +1 from me. I'm accepting this answer because of the details of the refinement process and how various geometries were tested. \$\endgroup\$ – cr1901 Apr 6 '17 at 1:30
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Transistors were miniaturised in a very incremental process.

For instance, you ask about TTL. The first 7400 quad NAND gate was at its time considered a feat of integration. There had been many iterative steps before that experimenting with smaller transistors, and connecting multiple transistors together with other passive components. The dimensions were relatively large, so light diffraction was a negligible source of error.

MSI, things like TTL counters, the 74161 for instance, was made by cut'n'pasting multiple gates together. The light tables were used to overlay a common, known, transistor layout on transparent plastic over each gate. It would be trivial to check the dimensions of each gate from the alignment. The main human intensive job was checking the connectivity.

The industry moved with stepwise refinement, steadily smaller geometries, steadlily larger integration, but all the time staying within something that could be cut'n'pasted, and was possible to check. Obviously overlays could check only small areas. EDA tools simply increased the area and the complexity that it was possible to check with confidence in a few weeks or months. I don't know exactly where the 6502 was on that route.

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How did they build locomotives before cad-cam?

Before computers it was about math, skill and experience, and in a lot of cases, trial and error. A lot of mistakes had to be made to obtain said skill and experience.

In the early days, integration was also not very large, so some of the finer points were not so critical.

As we have progressed a lot of that "skill and experience" has been programmed into the computer toolsets that are now available.

Whether we have gotten smarter as a result of that is questionable. Who remembers peoples phone numbers these days?

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People with Exacto knives were paid good bucks to carefully convert schematics into layouts. There were lots of opportunities to optimize performance, because the designer/engineer and layout person had hands-on access to the emitter and to base and to collector and to deep-well contact locations. Standard cells were optional; sharing pieces of layout, to reduce parasitics, was a trick used.

To verify, the layout, after being digitized at Gerber or Calma workstations, was printed out on 6' by 20' sheets and hung on the wall. Bribes/beer was given out for finding errors.

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  • \$\begingroup\$ This was the technique used for the very first chips designed at Atari, Apple and Amiga. Verification was done by having one engineer look at the tape and read out each wire and transistor and their approximate size, and having another technician draw schematics from that verbal readout. This was done small sections at a time. Minimum spacing was checked by eyeball with small metal rulers. Then the new small schematic was compared with a portion of the original large schematic and transistor size documents for possible variance. If OK, then the larger schematic was highlighter marked. \$\endgroup\$ – hotpaw2 Apr 14 '17 at 23:13
  • \$\begingroup\$ The circuit design engineers would use spice via remote system and teletype terminal. They would set minimum spacing and generic sizing rules, layout designers would try to copy and re-use various gate layouts that had been previously checked by the engineers to avoid having to rip up and re-do rubylith tape due to rule violations. Not completely standard cells, but a similar result. \$\endgroup\$ – hotpaw2 Apr 14 '17 at 23:24

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