I'm reading a history of EDA for ASICs because I'm curious about how older ICs were mass-produced.
The article explicitly mentions that in the early 1970's, SPICE was used to simulate circuit behavior, and cut rubylith was laid out to ensure that the ASIC design matched the schematic correctly (layout versus schematic):
What we now know as physical design verification consisted of taking flatbed plots of the layouts, pinning them on the wall or laying them on a light table, and having people try to find errors. Hence, physical verification was one of the first businesses to be adopted in the emerging custom design space (see "The More Things Change, The More They Stay The Same,").
However, the article doesn't really go into how designers ensured that ASIC features such as gates, would work correctly when the layout was shrunk to create a mask. Assuming an ASIC mask mistake was comparatively expensive in the past as it is today, what techniques were used to minimize the risk of a defective mask due to improper physical dimensions of features, such as a gate?
Considering geometry is important for an ASIC, were predictions of field strength using Maxwell's equations typically used (analogous to a 2.5D field solver for PCBs today), or were simple transistor models based on length and width sufficient? Or were physical dimension tolerances sufficiently large as to not be a significant source of error during manual layout?
To reduce the scope of the question, let's assume digital ASICs of the era such as TTL or 6502.