I'm using Altium Designer Winter 09 to synthesise a design for an FPGA. This includes a VHDL-defined entity
MyShifter that includes
generic parameters so I can have it be reuseable:
library IEEE; use IEEE.Std_Logic_1164.all; entity MyShifter is generic ( data_width : positive; pad_width : positive ); port ( -- ...other ports... DataIn : in std_logic_vector(data_width-1 downto 0) ); -- architecture follows...
With any other VHDL entity I could just right click on a schematic and use
Place » Sheet Symbol, and then synchronise the sheet entries with the ports defined in VHDL. Altium will, later on, automatically generate the higher-level VHDL that maps ports to other ports and I don't have to worry about it.
When I try this with my entity-with-generics, I end up with sheet entry labelled
DataIn[-1..0]. This is unsurprising, since I haven't "told" Altium what
data_width actually is.
My question is: how do I tell Altium what the generic parameters
pad_width are for a particular instance of