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I wish to know how to determine what happens when the logic output of an IC becomes shorted to VCC (preferably without actually having to short it). I realize that there are a plethora of ICs out there, all with different properties. I have chosen to use the 74HC74PW so that I have an example datasheet to talk about. I also wonder about AND gates, shift registers, etc.

Consider the example circuit below:

schematic

simulate this circuit – Schematic created using CircuitLab

SW1 is there to simulate a pin-short or other similar failure.

Hypothetically speaking,

  • If SW1 closes while Q is HIGH, then I'll assume no issue because VCC and Q are at equal potentials.

  • If SW1 closes while Q is LOW, then what process should I go through to determine the outcome?

Brainstormed ideas (while Q is LOW):

  • Q is low impedance, and V1 essentially shorts to GND. V1 and or the IC will be damaged.
  • Q is high impedance, the IC is essentially unaffected, and the micro simply sees the wrong value (HIGH).
  • Q is "medium/high" impedance. V1 is okay because it can supply ample current, but the IC is either damaged or effected in some negative way.
  • Something else?

The following table is from the flip flop's datasheet:

limiting values from flip flop datasheet

Am I able to determine the failure outcome from that table?

I have come across many ICs that don't disclose explicit output current or output clamping current though, so I'm wondering if there is a more general rule I could assume true when I the datasheet isn't helpful. (Perhaps I should assume all logic outputs are low impedance?)


What specifically should I be looking for in an IC's datasheet, how should I analyze it, and what other rules can I use when the datasheet doesn't have said info?

I imagine that relying on simulation software is risky for these kinds of conditions. I also don't want to rely on actually shorting the IC myself, because even if there appears to be no issue, it doesn't mean that there isn't one (especially over long periods of time).

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    \$\begingroup\$ Aside: your thought experiments on what might go wrong are part of what we call FMEA in industry - Failure Mode Effects and Analysis - and is an important part of the design of high-reliability circuits. As you've also figured out, you often need experience to predict what can happen in some of the hypothetical situations being considered - sometimes you need to actually do the experiment and observe the outcome. \$\endgroup\$ Commented Apr 5, 2017 at 14:59
  • \$\begingroup\$ What did that flip-flop do to deserve such abuse. Did it flip you off? \$\endgroup\$ Commented Apr 5, 2017 at 15:00
  • \$\begingroup\$ @AdamLawrence - My issue is that I don't want to rely on a test case because the absence of evidence is not the evidence of absence. \$\endgroup\$
    – Bort
    Commented Apr 5, 2017 at 15:00
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    \$\begingroup\$ Sometimes you need to do the experiment - once - then rely on it for future FMEA work. It is implausible to build enough samples to test all the conditions every time, and much of how the circuitry behaves is dependent on IC design and parameters which may not be well specified - experience is your only aid in this case. \$\endgroup\$ Commented Apr 5, 2017 at 15:02
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    \$\begingroup\$ You should look farther down the datasheet to the Recommended Operating Conditions and Static Characteristics sections to determine what might happen under your fault conditions. The "Limiting Values" (also called "Absolute Maximum Rating") table gives the conditions beyond which the device may be damaged - those values should never be met in normal operation. \$\endgroup\$ Commented Apr 5, 2017 at 16:19

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Philips NXP Nexperia has the HC(T) User Guide, which shows in figure 33 what happens when you overload an output:

HC output characteristics

So the outputs will not go above a certain current. But it's still too high.

This shows typcial values, not the possible maximum, but even so it certainly exceeds the IO limit of 25 mA that can immediately damage the chip.

Actually, this graph is for 4.5 V. There is another graph for 2 V, where the current stays below 10 mA, so you have to measure what happens at 3.3 V.

Anyway, the guide says in section 8.2:

The maximum rated DC current for a standard output is 25 mA and that for a bus-driver output is 35 mA. These ratings are dictated by the current capability of on-chip metal traces and long-term aluminium migration, but it is expected that output currents during switching transients will, at times, exceed the maximum ratings.

A shorted output will also cause the maximum DC current rating to be exceeded. However, one output may be shorted for up to 5 s without causing any direct damage to the IC.

The life of the IC will not be shortened if not more than one input or output at a time is forced to GND or VCC during in-circuit logic testing (“back drive”) as long as the following rules are obeyed:

  • maximum duration : 1 ms
  • maximum duty factor : 10 %
  • maximum VCC : 6 V

Please note that shorting an output for 5 s will not cause "any direct damage", but this implies that there will be indirect damage that will shorten the life of the IC. To avoid that, you'd have to keep the duration of the short below 1 ms.

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CMOS is made from Nch and Pch devices with a designed RdsOn which was ~300 Ohms for CD4000 series at 15V and 50 Ohms nominal for 74HC' series and 25 Ohms nominal for 74ALC' series with a wide tolerance. This limits short circuit current and also affects transition current spikes with capacitive loads but generally optimized for speed and controlled impedance tracks at max speed using 50 Ohms approx.

Use the specs for Vol/Iol to get these for logic "0" and (Vcc-Voh)/Ioh for a logic "1" on P-channel. There are some thermal and Vcc effects on RdsOn just like MOSFET switches, just as Vgs affects RdsOn on ~1V threshold switches.

From this understanding if you estimate effects of load impedance using impedance divider relationship. Normal logic ignores since it is high R but C values affect slew rate with RdsOn*C time constant, where C is internal, stray L,C in layout and input C of loads.

enter image description here

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(If the datasheet specifies Iol(max) and Ioh(max) separately, you're interested in Iol(max) for pins shorted to VDD, or Ioh(max) for pins shorted to GND. If the datasheet specifies Io(max) or similar, it's the same value for driving high or low. I'll call the relevant one Iomax here.)

The output will deliver a current of at least Iom. However, the datasheet value specified is the maximum current it can always deliver from every one of these ICs they make, so it's value is really the "lowest of the maximums". The actual current out of each individual IC (Ioactual) will be somewhat higher.

This causes a power dissipation in the totem-pole output's high or low transistor. So this can be predicted to be (Iomax x VDD) watts but is really (Ioactual x VDD) watts for each IC.

It then depends on how long the design and structure of that IC can handle that very localised power dissipation in that transistor before it's damaged or destroyed.

As an aside, I used to use 74LS and other 80's logic chips and if I inadvertently shorted outputs or connected logic outputs together, the chip would almost always be damaged and need replacing. Many modern logic ICs seem to be very tough, relatively speaking, and I've shorted out FPGA pins, memory chips I/Os and such like for minutes before realising my mistake and they've survived and lived long and happy logical lives. Not what I'd bank on in production but from a lab' playing perspective, they're pretty bomb-proof to me.

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General rule is... Never attach an output pin to either rail....

Clamping current is the maximum current the protection diode on the pin will withstand if you try to drive the pin with a voltage outside the supply range of the device. You can ignore that in your current question.

If you tie a driven pin to a rail you will definitely exceed Io, and ultimately damage the device.

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In this case, the maximum output current is ±25 mA which is basically how much current that output can withstand without damage. If you short Q to VCC when it is high, nothing much will happen. If you short Q to VCC when Q is low, you will be sinking a pretty high current through the output devices on Q, which will cause damage to the IC.

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Generally not a problem: the drive capabilities of those chips are fairly limited

However, if you tie a lot of to vcc or gnd, or they have significant current drive, it can be a problem.

Instead, use a resistor.

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    \$\begingroup\$ Not a problem? I'd predict bad things for the device. \$\endgroup\$ Commented Apr 5, 2017 at 15:22

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