Sample rate noise on SAR ADC

Question

I am diagnosing a legacy design that uses an AD7862 SAR ADC.

• Input is 500 Hz, 2.4 Vpp sinusoid, relatively low noise.
• Digitized output adds a noise component waveform +/- ca 0.25 Vpp.
• The FFT spectral peak (7484 Hz) of the noise is close to the sample rate, 7782 Hz. I expect a small amount of sample rate noise, but not this extreme amount. The noise waveform appears sinusoidal as well, not as a typical quantization.
• Of course I can FIR it after the fact, but would rather find root cause.
• The digital control signals to ADC are ringing to the point where they almost reach V(INH) and V(INL) thresholds. Could be false triggering? Affecting the SAR process? Otherwise digital signals are nominal.
• Happy to share diagrams, etc.

Answer 1

Interface Noise, from the digital side, can set a floor, as you have seen. Cure?

The MCU rings, because 1nanosecond clock-charge surges abruptly discharge the onchip charge-bucket, the various parasitic well-substrate capacitors and any unused FET gates in the quiescent logic/flops/memories. This abrupt sag of VDD (and rise of GND) in the MCU will appear on the interface signals to the ADC. Ringing will be approximately 100MHz, perhaps 200MHz. We'll use 100MHz at +-1volt. The slewrate is d(1*sin(100MHz*2pi*t))/dt = 628 MegaVolts.

All your interfaces signals, even "quiet" levels, will have this trash and this slewrate.

Your ADC ESD structures, between 3pF and 10pF in size, response to these changing voltages, and currents flow; those currents need to return home, back to the MCU, and those currents explore all possible paths, including out the analog signal inputs from your sensor. Most of the current goes out the lowest impedance path, the ADC VDD and GND, thru those inductances. Those inductances ring because of the onchip well-substrate capacitances.

^{simulate this circuit – Schematic created using CircuitLab}

Solution? slow down the edges and reduce the amplitude of the currents. How? insert resistors (1k or 10K) in the interface lines, and add 100pF caps at the ADC side of the interfaces.