# Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the logical effort of a logic gate tells how much worse it is at producing output current than is an inverter, I am confused here. With two inputs active in the NAND gate shouldn't the logical effort be low. Also, when we use logical effort to estimate the minimum delay for a multi-stage system why do we use 4/3 as the logical effort for a nand stage (which is just the effort of one input) ?