So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the logical effort of a logic gate tells how much worse it is at producing output current than is an inverter, I am confused here. With two inputs active in the NAND gate shouldn't the logical effort be low. Also, when we use logical effort to estimate the minimum delay for a multi-stage system why do we use 4/3 as the logical effort for a nand stage (which is just the effort of one input) ?
Intuitively Logical Effort is proportional to the amount of "work" needed to propagate a signal through a gate. One way this "work" is done, is by charging the gates of the mosfets to turn them on. So in the case of 2 inputs active, you are charging two gates and hence moving twice the amount of charge to achieve this, therefore Logical Effort increase.
When estimating delay you can do it for one path(from desired input to output) at a time, so unless you are splitting the path and applying it to the same gate(which is redundant and wasteful in terms of logical effort), you always use "effort of 1 input"