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I'm working on an adjustable (0.1 - 60VDC) direct off-line SMPS using UC2843.

Expected minimum output voltage is 0.1VDC in my application, so the minimum duty-cycle ratio (\$D_{min}\$) will be %0.08. Since the gate drive signal is not perfectly rectangular, it will have sharp triangular pulses at such low duty-cycle ratios. I think that it's impossible to drive a MOSFET with such a signal but I'm not sure. Gate capacitance of the MOSFET is about 1.5nF, by the way.

According to the datasheet, UC2843's rise- and fall-times (\$t_r\$ and \$t_f\$, respectively) are about 50ns typical. Putting minimum \$2t_r\$ between rise and fall for proper driving (which means \$t_{on-min} = 4t_r = 200ns)\$, required switching frequency will be about \$f_S=8.10^{-4}/200ns = 4kHz\$. :) Of course the switching frequency cannot be that low. I'm planning that it will be around 100kHz.

Is it safe to drive a MOSFET with a "triangular" pulse? If not, what can you suggest?

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You should be fine with such a low duty cycle and one that is triangular shaped. If the duty cycle were greater there would still be a ramp up and a ramp down but, at very low duty these will be the main losses so, providing your MOSFET can handle large duties then it should be perfectly ok at low duties.

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  • \$\begingroup\$ Thanks for your answer. Since the application is a DC-DC converter, switching frequency will be 100kHz. Is it still be fine to drive the MOSFET even with that high frequency and extra low duties? \$\endgroup\$ – Rohat Kılıç Apr 7 '17 at 9:23
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    \$\begingroup\$ If the circuit works ok at middle duties then it will work ok at low duties even if the pulse shape is triangular. It won't harm the mosfet but the output will be less linearly related to pulse width at low duties and, for really low duties (hard to say how low) the output voltage will tail off to zero. If you have feedback and duty control this won't matter. \$\endgroup\$ – Andy aka Apr 7 '17 at 9:29
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The UC2843 is a current-mode controller. Its minimum pulse width is dictated by the propagation delay (it's the part internal logic delay plus the the time needed to effectively turn the MOSFET off when the CS pin "sees" the current setpoint programmed by the CMP pin) to which you add the contribution of the Leading Edge Blanking (LEB) circuit. This LEB is a simple \$RC\$ circuit installed between the sense resistance and the CS pin of the 2843. It is there to blank (or hide) the current information supplied to the CS pin during the first hundred of nanoseconds when the MOSFET turns on. During that short period of time, the CS pin may see a large-amplitude peak due to the stray elements in your circuit (MOSFET input capacitance, output diode \$t_{rr}\$, drain lumped capacitance etc.). Because you do not want your UC2843 to react to this parasitic peak, you insert this LEB circuit. Typical values are \$1\;k\Omega\$ and a small capacitor like 100 pF. This time constant will affect the minimum on-time the circuit can produce so you must tweak it to get a clean signal at CS but not oversize it otherwise you won't obtain small duty ratios. For noise reasons, keep the LEB \$RC\$ circuit very close to the controller while the signal bringing the current information naturally being of low-impedance nature (\$R_{sense}\$ is low) can be a longer trace. Also, keep the lowest impedance drive for the MOSFET, especially if you drive a large-\$Q_g\$ type of device. If the drive signal is too triangular (meaning you don't have enough current to turn the MOSFET off and on quickly enough), you will generate unacceptable losses. Finally, the UC2843 can go to 0 duty ratio so in case the IC cannot reduce the on-time low enough, your loop (provided you are operating in a closed-loop configuration) will force a so-called skip-cycle operation during which the controller "skips" switching cycles because the CMP pin is too low. I don't know the topology you use for that power supply, but you know that tapped-versions of boost or buck can help increasing the minimum duty ratio for the same dc transfer function. Also, an isolated (or non-isolated) circuit featuring a transformer may be a more convenient option.

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  • \$\begingroup\$ Thank you for your answer. I am not new to SMPS design. I have designed a lot of isolated offline converters with various power and topologies. But this is the first time I encountered that kind of "problem"(or whatever). Anyway, the topology is two-sw isolated forward converter. I will put a totem-pole to drive both switches so the driver's output impedance will be quite low. I will try and see the results. If I don't get a good performance, I will put a pre-regulator first (say, 80VDC) then I will put the adjustable block after this so that the duty never be that low. Thanks again. \$\endgroup\$ – Rohat Kılıç Apr 7 '17 at 18:52

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