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how to short SMD pads?

Which of the three ways shown above would be the best way to short two adjacent SMD pads together, and why? These are TSSOP pads and the assembly process will be lead-free reflow, if that matters. If there are better ways that I have not pictured, feel free to show them too.

I can imagine that in terms of impedance, C is best and A is worst. But I'm not sure if C or even B could somehow complicate the assembly process.

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    \$\begingroup\$ I've always been taught to do it the A way, though I'm afraid I can't remember what problems B would cause. \$\endgroup\$ – Federico Russo Apr 11 '12 at 17:42
  • \$\begingroup\$ Compared to var. A, there's less space used on the PCB; compared to var. B there's less impedance between the two pads. \$\endgroup\$ – m.Alin Apr 11 '12 at 17:52
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    \$\begingroup\$ @m.Alin what about solder flow? (Note that this is a question, not a sarcastic comment!) \$\endgroup\$ – exscape Apr 11 '12 at 18:01
  • \$\begingroup\$ @exscape I overlooked that aspect \$\endgroup\$ – m.Alin Apr 11 '12 at 18:12
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There are two issues here, the electrical connection and the thermal connection.

The best electrical connection minimizes the impedance between the two pads. From that point of view, the order of preference is C, B, A.

The best thermal connection has the most thermal resistance, so the order of preference is A, B, C.

As with most of engineering, it's about making the right tradeoff for the specific case after considering the relative advantages and disadvantages of each. We therefore need to understand the reason for each of the competing considerations and how much the result matters.

The desire for low electrical impedance should be obvious, but how much does it matter? That depends on what will flow between the two pads. Is this a a multi-GHz signal, like going to or from a WiFi antenna? In that case, even a few nH and fF could matter and the electrical considerations become important. Is this a high current feed? In that case the DC resistance matters. Most of the time for ordinary signals of the kind you'd find around a microcontroller, even the impedance of layout A will be so low as to not matter.

The thermal conductivity issues depend on how the board will be built. If the board will be hand soldered, then layout C makes a large heat sink such that it could be difficult to keep the solder molten accross the combined pad. It will be even worse when one part is installed and the other not. The first part will act like a heat sink making it difficult to heat the pad to install the second part. Eventually the solder will melt, but a lot of heat will have been dumped into the first part. Not only is that asking for errors when manually soldering, but it could be bad for the part to be heated that long.

If the board will be stuffed by pick and place with solder paste and then oven reflow soldered, then there is no issue of one pad sucking heat from the other since they will both be heated. In that sense layout C is OK, but there is another problem. That problem is called tombstoning, and happens when the solder melts at different times at the ends of small and light parts. Molten solder has much higer surface tension than solder paste. This surface tension on one end only of a small part can cause the part to release from the other pad and stand up on the pad with the molten solder. This standing up at right angles from the board is where the term tombstoning comes from, like a tombstone sticking up from the ground. This is generally not a problem at a size of 0805 and up because the part is too long and heavy for the surface tension at one end to lever it up. At 0603 and lower you need to think about this.

There is another thermal issue though, and this applies to large parts too. The surface tension of the molten solder on each pin pulls that pin towards the center of its pad. This is one reason small alignment errors in placement don't matter. They get straightened out during reflow by the combined suface tension on all the pins trying to average out the center placements. If a part connected to pad C at one end has a normal pad at the other, it could possibly be pulled towards the center of pad C and off the pad at the other end. You could compensate for this a bit by making a special footprint with the other end pad closer than it would normally be so that some pulling is OK. I would only play that game if I really really needed layout C, which I can only imagine in a high current or high frequency case.

Using the normal solder mask shapes for pad C would get around the part-pulling case. There would be two separate solder mask openings on pad C with a section of solder mask between. The surface tension would pull to the center of each solder mask opening, not to the center of the whole pad C. This doesn't fix the tombstoning problem for small parts though.

In general, I'd use layout B unless I knew of a good reason to use A or C.

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    \$\begingroup\$ One thing to consider is that A is best for any situation where you may need to cut the trace for debugging purposes. B would be very hard to cut once the PCB is populated, and C would be a nightmare. \$\endgroup\$ – Connor Wolf Apr 11 '12 at 21:32
  • \$\begingroup\$ @Fake: Actually B should be pretty easy since the parts from the two pads aren't over it. However, I agree about C. You would have to unsolder one of the parts and edit the circuit from there. \$\endgroup\$ – Olin Lathrop Apr 11 '12 at 21:59
  • \$\begingroup\$ that depends on the pin pitch, and whether it's a SOIC or (S/T)SOP, which would be accessible, or a QFN/PLCC, where it wouldn't be accessible. \$\endgroup\$ – Connor Wolf Apr 11 '12 at 23:24
  • \$\begingroup\$ @Fake: It should be accessible either way since the parts on the two pads don't abut. All you need is enough room to slide a utility knife the parts. Also, from the shape of the OP's pads, this is no QFN package. \$\endgroup\$ – Olin Lathrop Apr 11 '12 at 23:41
  • \$\begingroup\$ For a moment I was also thinking of tombstoning, but from their shape these seem to be QFP pads, and then that doesn't apply. \$\endgroup\$ – stevenvh Apr 12 '12 at 5:42
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Someone once said something like: Ask 2 electronic designers, get 3 answers. :-).

high-current pins

When I have a device that handles high currents -- perhaps it's a motor driver or a voltage regulator -- then I connect the biggest possible traces to each and every every constant-voltage or slowly-switching pin -- type C, or preferably even more copper.

low-current pins

Most TSSOP devices have inputs and outputs that are digital signals with almost insignificant amounts of current. With these devices, I much prefer an easy-to-access loop like type A for my first prototype board.

Then, if I've connected something that shouldn't be connected, it's easy to cut that loop and connect each pin to something else.

After I get the prototype working (which always seems to take longer than I expect), while it wouldn't hurt anything to convert them to type-B, why bother? I usually don't bother, so my final production boards often have such type-A loops.

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I prefer A for a clarity reason. With A you can clearly see that those pads are supposed to be bridged. Yes, it takes up more valuable PCB space, in which case B or C are perfectly acceptable, however I would prefer C over B for debugging purposes.

If you have a single trace like B between two pads, unless you have a good microscope it looks like there is something trapped in there when you look at it with the naked eye. Part of my job is hardware troubleshooting and I have seen our hardware designers do all three.

A is by far the easiest to read; C is next because that giant pad makes it clear to the naked eye that they are supposed to be bridged; and B is my least favorite because I always end up having to pull out a scope to see it properly.

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    \$\begingroup\$ Next to human optical inspection / rework, A is best (and maybe the only solution) if your manufacturer uses AOI (automatic optical inspection) or AXI (automatic x-ray inspection). B might look like an untintentional solder blob. So does C. With A, you can easily tell what's going on as far as excessive solder is concerned. \$\endgroup\$ – zebonaut Apr 12 '12 at 8:15
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Often the solder mask is pulled back between the pads of B (depends on pad spacing and soldermask relief values), exposing copper between the pins. This results in what looks like a solder bridge which can be a bit disconcerting during visual inspection and debugging.

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