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I have built the following N-MOS & P-MOS push-pull dual MOSFET circuit. Its purpose is to control some external LEDs from a 3.3V microprocessor.

However, there seems to be a problem, where the dual MOSFET chip “SI4554DY-T1-GE3 Dual N/P-Channel” dies a horrible fumy smoke death, when 12V is connected as shown in the schematic below.

The smoke appears even when no load is connected and the MOSFETs are not switched (idle).

As far as I can see in the datasheet, none of the limits (V[GS] < 20V, V[DS] < 40V) are exceeded.

Can you help in identifying the problem? Thank you!

schematic

simulate this circuit – Schematic created using CircuitLab

Image of the circuit implementation

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    \$\begingroup\$ What is the gate voltage when you connect 12V? Probably both mosfets are conducting, shorting each other. Also, why are you using push-pull for this? The N-mosfet isn't doing anything useful in driving your LEDs... \$\endgroup\$ – marcelm Apr 7 '17 at 12:41
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    \$\begingroup\$ When you apply power, you're relying on R2 to charge up the gates of the two MOSFETs. How long does this take, and how much current flows through them in that time? \$\endgroup\$ – Dave Tweed♦ Apr 7 '17 at 12:42
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    \$\begingroup\$ Are you able to add a switch between 12 V and where it powers M1? That ways, you could bring up the 12 V supply and let it stabilise and the gate drive stabilise before you power the push-pull circuit. That would rule in or out the slow rise time of the PSU leading to both devices conducting at once. I would also try reducing the 47 K pull-up to 4K7 for a much sharper rise time while it charges the gates, though I think that's less likely the cause. \$\endgroup\$ – TonyM Apr 7 '17 at 12:51
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    \$\begingroup\$ Probably has something to do with the 222A chugging through there when they are both on at the same time.. \$\endgroup\$ – Trevor_G Apr 7 '17 at 12:56
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    \$\begingroup\$ The part actually installed on the board is 51K. Why do people insist on showing us schematics that don't reflect the reality of their situation? The reference designators are all wrong, too. \$\endgroup\$ – Dave Tweed♦ Apr 7 '17 at 14:12
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Your Push-Pull configuration is inverted. N-channel MOSFET is supposed to be connected to +ve rail and P-channel MOSFET should be connected to -ve rail. Your circuit blows up because both the MOSFETs will turn on for some amount of time when input changes from low-to-high or high-to-low. This will cause short circuit and you will get the magic smoke!

Please see the reference link below:

http://www.talkingelectronics.com/projects/MOSFET/MOSFET.html

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  • \$\begingroup\$ I am certain that the design should be correct. I have used that push-pull design multiple times. The difference now is that I am using a component with dual MOSFET, compared to using individual MOSFETs in the past. Searching for half bridge mosfet driver, both designs seem to be popular. \$\endgroup\$ – Johis Apr 7 '17 at 13:26
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    \$\begingroup\$ @Johis there is a significant difference in the switching times of the mosfets. Even if you can guarantee the gate signals arrive simultaneously, there WILL be a "both on" time. I suggest you either drive the gates separately or add some inductance in the power line with a fly-back diode to cut out the spikes. \$\endgroup\$ – Trevor_G Apr 7 '17 at 13:34
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    \$\begingroup\$ @Johis, I feel daft because I looked at this earlier, when I checked your FET sources were connected correctly on your PCB. But your scheme would work...if your gates had really fast rise time and fall time. To avoid the problems of this, it's much better and just as easy to use the opposite scheme, shown by vivekkholia's links. That ensures that both FETs are off as the gates voltage transitions through the 'dead zone' between very-high and very-low. I was shown this on a motor drives a few decades ago, should have spotted it. \$\endgroup\$ – TonyM Apr 7 '17 at 13:41
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    \$\begingroup\$ @Johis if you have to use the same configuration you are using, then consider driving MOSFETs individually. Allow a dead-time to ensure they are not conducting at the same time. \$\endgroup\$ – vivekkholia Apr 7 '17 at 13:42
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    \$\begingroup\$ @WhatRoughBeast It was not simply wrong. It was probably irrelevant to the question asked. I also said some extra stuff before posting it. Removed it though. \$\endgroup\$ – vivekkholia Apr 7 '17 at 15:18
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Push pull-circuits of that design are notorious for fusing through due to inadvertently turning on both mosfets simultaneously.

Obviously, this can happen during switching, but it can also happen as the power is applied to the circuit. The current pulse is normally very short, however, the smaller the mosfet devices the more probable a failure will occur on one or both of them.

As such, when using rail-rail push-pull drivers like this it is required that some protection be provided to ensure that the current can not spike through the bridge.

Below is an example that uses an in-line inductor as a current choke.

schematic

simulate this circuit – Schematic created using CircuitLab

L1 and D1 in the schematic above should be sized to limit the rise time of the current to be significantly less than the switching time of the mosfets.

Resistor R2 should be included to force the circuit into a particular state while the logic that is driving it is powering up. This is especially true if the signal originates from a micro that is initially configured as a high impedance pin. Whether this resistor is pulled to ground of logic 1 will depend on which state you want the output to start in.

C1 is intended to try and protect the mosfets from any start-up voltage spikes on the power supply.

R1 should also not be over-sized. It needs to drain the capacitance of M1 and charge M2 quickly enough when the transistor turns off.

Ultimately, with this type of driver, it is preferred that separate control signals be used with a built in dead-time where both switches are turned off before one is turned on. In addition to giving you more protection for your driver, it also adds the functionality of being able to disconnect the output entirely.

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When you say 'testing with NO drive signal', do you mean "no drive" is low resistance ground or O/C.

If Vin is always high or low then Q1 state is defined.
But O/C Vin allows Q1 to possibly turn partially on - which can be disastrous.
Regardless, a highish value resistor from Q1 base to ground is in order - say 10K.

Several people have mentioned shoot through via M1 & M2 and several schemes have been proposed. POSSIBLY useful is a zener from Q1 C to each FET gate and a resistor per FET that turns each FET off from Gate to source.
2 x say 6V8 zeners on a 12V supply means that there is minimal crossover.

In the diagram below, assume V+ is 12V & FET Vgsth is 2V in each case.
FET lower required Vc to be at 2V + 6V8 = 8.8V or higher to turn on.
FET upper requires Vc to be at 12V - 8.8V = 3.2V or lower to turn on.

For Vin < 6.8V. FET lower is fully off.
For Vin > 12 - 6.8V = 5.2V FET upper is fully off.
This significant dead band protection MAY help prevent shoot through.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ I will test your suggestion and come back to you. The above test was with an open circuit at the base (since I assumed the leakage would not be sufficient to turn on the NPN BJT). \$\endgroup\$ – Johis Apr 10 '17 at 15:28
  • \$\begingroup\$ @Johis Before trying zeners etc, just add the base pull down. Leakage current is multiplied by Beta (at least) and increased collector current may occur "once it gets going". | This is definitely the source of problems in some cases. Whether it is so here is TBD. | NB - NEVER give Murphy an even break - he's quite capable of making trouble even when you do things correctly :-). \$\endgroup\$ – Russell McMahon Apr 11 '17 at 7:14
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12V and there is no current limit. Assume an incidence where both conduct for whatever reason and lead to failure. Put a current limit resistor in the supply or a resistor in the supply and a resistor to ground for output voltage balance within current tolerance of the device(s).

I am soon intending to experiment with dual gate (MOS) FETs' and this article has provided inspiration! Thanks :-)

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