# Index into std_logic_vector using signal

I need to modify a certain portion of a register, but the upper and lower bound of the modified part depend on the input. Can the following code:

(1) be synthesised?

(2) if so, what circuit do the tools produce?

reg (to_integer (unsigned(upper1)) downto to_integer (unsigned(lower1)))
<= input (to_integer (unsigned(upper2)) downto to_integer (unsigned(lower2));


(edit: the syntax might be wrong, but I hope I've got the idea across)

• Isn't it exciting to just try it? – Gregory Kornblum Apr 7 '17 at 16:22
• Hint: multiplexers.. – Eugene Sh. Apr 7 '17 at 16:22
• Any time you see that many type conversions, step back and declare things in the right type in the first place. – Brian Drummond Apr 7 '17 at 18:54

## 1 Answer

Yes, it is possible for every reg bit to be fed by any of the input bits as long as upper1, lower1, upper2 and lower2 are within the range of the respective vvectors.

Note that any reg bits that aren't specified by the range between upper1 and lower1 will be unchanged (forming a latch in a combinatorial implementation e.g. concurrent assignment or an unchanged output of a flipflop in a sequential design e.g. clocked process) and any of the input bits not covered in the range of upper2 to lower2 will be ignored.

As Eugene_Sh commented, it will be done using multiplexers.