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I want to be able to select between two clock signals, 16MHz and 1MHz, using an analog SPDT switch. Do I proceed correctly, by buffering these oscillators? Or is there a better way to do this?

The clock goes to the MCLK input of an AD5934, whose input capacitance I do not know, but I'm assuming it drives multiple circuitry inside the IC.

The analog switch has an input capacitance of 17.5pF, while the oscillators specify a maximum load of 15pF, that's why I assume a buffer is needed.

Is this the correct way to do such a clock switching?

enter image description here

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You can use what you have shown but personally I'd make a 2:1 logic multiplexer from 4 NAND gates: -

enter image description here

There are plenty of other options courtesy of google images.

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  • \$\begingroup\$ That is a really cool idea! Forgot about multiplexers. \$\endgroup\$ – Calin Apr 7 '17 at 19:38
  • \$\begingroup\$ FOX clocks will have 25~50 Ohm (RdsOn) CMOS drivers , so no buffering is needed, But due to fast rise times, adding capacitive loads reduces rise time and increases power consumption, so similar CMOS inputs such as Andy's NAND or MUX gates ought to be fine with 74HCLVCxx rated ~ 4.5pF input max and x pF per inch of trace length over a ground plane of trace capacitance. AD5934 is an interesting chip, not seen before. \$\endgroup\$ – Sunnyskyguy EE75 Apr 7 '17 at 19:54
  • \$\begingroup\$ Interestingly, I did not seem to find what exactly these oscillators ICs contain. I assume a Pierce oscillator, but that 15 pF max load is what scared me. \$\endgroup\$ – Calin Apr 7 '17 at 20:00
  • \$\begingroup\$ It's also a big surprise than ADI were very poor at specifying the input capacitance of the chip too. \$\endgroup\$ – Andy aka Apr 7 '17 at 20:09
  • \$\begingroup\$ @Calin you can figure this out yourself.... Ic=CdV/dt 3ns rise time avg on Fox spec with 15pF max Ic=? This current pulse limited by the 25~50 Ohm RdsOn CMOS driver needs to be absorbed by the low ESR decoupling cap near the Xtal IC in order to reduce 3.3V supply noise and general EMI reduction standard practice. (Answer: 16.5mA * 50 Ohms = 0.825V internal CMOS driver drop during dV/dt) which reduces step output pulse level until 15pF charge current expires by 0.8V . Thus modeling this once in your mind or on paper helps to explain without a 1GHz scope why they spec 15pF max or 50pF \$\endgroup\$ – Sunnyskyguy EE75 Apr 7 '17 at 20:25

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