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In that timing diagram we see that the write command in the same time nearly with the data. Why we don't see that also in reading data and why there is that delay between data and read command?

That is screen shot from ATmega328 datasheet page 36

enter image description here

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  • \$\begingroup\$ The diagram is probably more detail than Atmel (now Microchip?) needed to show. It's all internal and doesn't impact anything outside the chip. But they probably just wanted to "look accurate" and show that the read-data was latched at the falling edge of their internal RD line and that they held the data bus until after that edge. The read SRAM data would then have been successfully latched somewhere (like, in a register.) The write data cycle has no need to hold signals after end of T2 so they didn't show it. \$\endgroup\$ – jonk Apr 8 '17 at 0:52
  • \$\begingroup\$ @jonk ...I'd suggest you are completely wrong in your comment. A write clock transition requires address/data is setup before the transition ....and in a Read clock will latch the address and the data will arrive after the transition (and once the address has settled) \$\endgroup\$ – Jack Creasey Apr 8 '17 at 6:21
  • \$\begingroup\$ @JackCreasey I don't disagree with your comments. The diagram shows the address being set up ahead in both cases. I would suspect that latching of data for RD might be on the falling edge T2 and there would be no need for the way it's shown. Do you have some good thoughts to add to Kevin's? \$\endgroup\$ – jonk Apr 8 '17 at 16:39
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The delay is the read access time of the RAM.

In the case of writes the data comes from the ALU or other part of the CPU and is destined to be stored in RAM. The data has to be maintained until it has been stored in the RAM memory cells.

For reads the RAM logic does not start operating until it has the address as shown in the second waveform. First the address has to be decoded to enable the specific bit cells that contain the data. Then the data has to be sensed and communicated through the RAM data buffers. For the ATmega 328 this probably takes a few 10's of nanoseconds.

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