On many surface mount power N-mosfets I have seen that the large pad is electrically the drain pad.

Wouldn't it make more sense to heat sink to the ground plane, where you probably already have a lot of copper? It seems like making the "heat sink pad" drain just increases the amount of total copper/used space on the board. Why design them so that you have to add an additional, or perhaps many, separate large fill(s) for heat?

  • \$\begingroup\$ Normal Thru hole use Drain for tab just like BJTs use collector for tab.It would be convenient if the source was the tab in more cases than the drain .There were some olde school audio lateral N and P channel fets in TO3 metal packages that did have source as the case . \$\endgroup\$ – Autistic Apr 8 '17 at 5:25
  • \$\begingroup\$ Thermally it's a mistake to think ground plane matter to a power mosfet. \$\endgroup\$ – Gregory Kornblum Apr 8 '17 at 5:32
  • \$\begingroup\$ @Gregory Kornblum: Okay, but even if you are saying you are always going to be adding some kind of heat sink anyway, wouldn't it be much more convenient for that heat sink to be electrically ground? Attaching the "sink pad" to source would make it easier to attach an electrically grounded metal case (if case ground is the same as circuit ground). Or if you have a separate heat sink, you don't want it to be at a non-ground potential so this setup necessitates extra electrical insulation between heat sink and drain (which is inefficient and adds an extra part). \$\endgroup\$ – Jessica O Apr 8 '17 at 5:40

For the same reason that bipolar transistors are heat-sinked through the collector. When the transistor is made, that's the big terminal on the back of the die. The source, or emitter in BJT's, is a mesh of little terminals interspersed with the gate or base terminals on the top of the die. It's simply the only practical terminal to connect to.


Because the heat sink forms a parasitic capacitor. When the mosfet switches large currents can pass through it. If you ground it, you have just improved its capacitance due to the larger area of the ground plane. Now it can also couple to anything within the guard ring of the MOSFET. If you connect the heat sink to the source, it will be directly connected to the power planes too.

Treat the heat sink as you would treat an enclosure. You do not connect a conducting enclosure directly to ground at multiple points in order to prevent current paths. You use capacitors to block the current loops. This is why you use a separate plane for thermal dissipation and connect it to ground through capacitors for EMC (RF bonding). A more detailed discussion can be found here.

P.S. For fast switching applications the heat sink can sink/source significant current, even if it is floating. I've seen circuits with a few amps going through it.

  • \$\begingroup\$ And why should it be beneficial to put that parasitic capacitance at the drain instead of source? \$\endgroup\$ – Junius Apr 8 '17 at 7:03
  • \$\begingroup\$ @Junius because the source is directly connected to ground (or power). This directly connects the heat sink to the power planes. Now the heat sink can use the entire power plane as discussed in the answer. If the heat sink is connected to the drain instead, you can use a separate plane for dissipating heat and connect it to the ground plane through capacitors for EMC purposes. \$\endgroup\$ – user110971 Apr 8 '17 at 7:11
  • \$\begingroup\$ Hm, that's interesting. I have never thought about that. Still, i don't see that much applications where decoupling capacitors are placed at the drain because if you want to switch anload fast that that capacitance actually slows down the switching progress and therefore increases power losses? \$\endgroup\$ – Junius Apr 8 '17 at 7:21
  • \$\begingroup\$ @Junius you use tiny capacitors. You need to decouple the high resonant frequencies of the heat sink in order to prevent it from acting as an antenna. This generally does not affect the switching speed of the mosfet. \$\endgroup\$ – user110971 Apr 8 '17 at 7:30
  • \$\begingroup\$ Do you have some application note or reference circuit where what you suggest is done in practise? I don't know circuits where EMC related caps are located directly at the drain but rather after some kind of snubber or clamping circuit... Would be interesting for me though! \$\endgroup\$ – Junius Apr 8 '17 at 14:17

For improved thermal management, attach the heat-removal path to the region of the silicon where heat (I*V) is generated. Silicon thermal conductivity is 150 watts/meter * degree C. For a cubic meter of silicon. For a cubic centimeter, the heat travels only 1cm but the area to conduct the heat has dropped from one square meter to 0.01*0.01 square meter. Result is thermal conductivity drops to 1.5 watt/ degree C ----- if the heat has to travel that entire centimeter. Silicon wafers are 300 microns (0.3mm) thick, thus ThermCond is 5 watts/degree C. By removing heat nearest its generation region, we can cut that in half. But that results in floating heatsinks.

What happens when the heatsink is floating, and moving with some slewrate?

How severe is that transient current from heatsink to "ground"? and what deltaVoltage across a 10nH inductor? (1cm of return path)

Assume heatsink 10cm by 5cm; assume 20 mils between layers, or 500 microns. Assume Er = 5. Capacitance C = E0*Er*Area/Distance becomes

9e-12 * 5 * 10cm*5cm/0.5 millimeters = 45e-12 * 50 *0.0001 / 0.5 * 0.001 = 450pF

Assuming 200 volts in 200 nanoseconds transient on the FET drain.

I = C * dV/dT = 450 pF * 1e+9 = 0.45 amp, with Trise of 10 nanoseconds (the FET likely turns on in 10nS, though the slewing lasts for 200 ns).

What is the "ground" upset? V = L * dI/dT = 10nH * 0.45amp/10nSec = 450 milliVolts


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