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I'm learning about the different memory access modes for SRAM. (Specific datasheet available here.) As I understand, there is "asynchronous mode", "page mode" and "burst mode".

Page mode is an extension of asynchronous mode to efficiently deal with adjacent read accesses. Page 12 says that such a page mode does not exist for write accesses.

Why do we not have page mode write accesses? Are there any fundamental restrictions for such write accesses?

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Yes, there is a reason you can't do a bunch of writes together. In reads you can change the address while the output is enabled and the only problem is the time for the data to settle. For writes if you change the address while write enable is low (and it is level-sensitive), you would write to other addresses since one bit would change before another.

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  • \$\begingroup\$ One could design a chip for use with "gray coded" address changes (i.e. write four bytes where the LSB's go 00 01 11 10). I expect that, in practice, many asynchronous SRAMs would be perfectly happy and reliable if driven in that way, though I don't think I've seen any specified as allowing it. \$\endgroup\$
    – supercat
    Apr 13, 2012 at 20:47

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