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This circuit is equivalent to small-signal common source JFET amplifier:

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If you look at the input and output impedance you can see that Zin = R1 || R2 and Zout = rd || Rd || Rl. It can be seen from the small-signal model.

But shouldn't small-signal model look like this?

enter image description here

I just want to understand these models and maybe derivate input and output impedance myself.

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The ideal DC voltage source has 0Ω internal resistance. And that's why AC-signals are shorted by DC voltage source. DC voltage is always constant so for any change in current there is no change in the voltage. So there is 0 Ohm internal resistance. Additional in real life circuit we always uses a bypass capacitor connect parallel to DC Voltage. And this capacitor will short all AC-signal to the ground.

For example if we have a 9V DC voltage source, now if we smoothly change the current that is draw from this DC voltage source, from 40mA to 20mV (we change the resistance from 225Ω to 450Ω). We create AC-current. But the DC voltage do not change (0Ω internal resistance). So the dynamic resistance of DC-voltage source is equal to rd = 0V/20mA = 0Ω And this is why we say that DC-Voltage is a short for an AC-signals.

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  • \$\begingroup\$ But we deal with ideal parameters only in theory. In practice the voltage source will have some resistance and therefore models like this one do not apply in practice - I mean, the formula for input/output resistance does not apply in practical situation. Or does it? \$\endgroup\$ – Keno Apr 9 '17 at 16:50
  • \$\begingroup\$ In normal situation we use bypass capacitor across supply rails to reduce (bypass/short) the voltage source internal resistance. So do not worry abut this anymore \$\endgroup\$ – G36 Apr 9 '17 at 17:06
  • \$\begingroup\$ Its only that it doesn't seems logical to me if I am considering the basic electronic principles... Looks like I'm not ready yet to understand all of this you were explaining about. \$\endgroup\$ – Keno Apr 9 '17 at 20:07
  • \$\begingroup\$ @Keno What thing is not logical to you? Can you elaborate? \$\endgroup\$ – G36 Apr 10 '17 at 3:31
  • \$\begingroup\$ The thing that Vdd becomes ground in small signal models. \$\endgroup\$ – Keno Apr 10 '17 at 17:32
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DC sources are always grounded in small signal analysis and therefore you get R1 || R2.

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  • \$\begingroup\$ But why are they grounded? For simplicity of equation derivation of what? \$\endgroup\$ – Keno Apr 9 '17 at 16:42
  • \$\begingroup\$ Since you said DC sources are always grounded in small signal analysis, does that mean the Udd represents ground for AC signals? \$\endgroup\$ – Keno Apr 9 '17 at 16:47
  • \$\begingroup\$ Yes, Udd represents ground for AC signals. \$\endgroup\$ – G36 Apr 10 '17 at 18:57
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schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ I'm a sincere admirer of your ability to use CircuitLab to draw almost everything. \$\endgroup\$ – Enric Blanco Apr 9 '17 at 13:30
  • \$\begingroup\$ Help me on this. How can these be made more clear? \$\endgroup\$ – analogsystemsrf Apr 9 '17 at 20:58

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