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I have an ARM microprocessor connected to an FPGA through one 47 pin memory bus. Also, two identical PSRAMs (datasheet available here) are connected to the FPGA through 65 pins (47 for first PSRAM + 16 extra data pins for the second PSRAM + 2 extra control pins for the second PSRAM).

For emissions testing, I would like to drive both PSRAMs at the same time, and at full speed. However, to drive both PSRAMs independently at the same time, I would need 65 control pins between the ARM and the FPGA, but I only have 47.

I was thinking that I could drive both PSRAMs at the same time and in exactly the same way by routing the 18 extra pins for the second PSRAM to the first PSRAM.

However, there are two potential problems I am seeing:

  1. The WAIT output signal for both PSRAMs might not behave the same way, and I do not see an obvious way to combine the two WAIT signals into one.

  2. When the ARM makes a READ request, there is a possibility that both PSRAMs will not return the same value on their data buses, which means that the combined data bus will be driven by both the PSRAMs in different ways.

Are there other problems I haven't considered with routing the pins of two different PSRAM to the same controller? Are there solutions to the two problems above?

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  • \$\begingroup\$ See data sheet page 26 e loading. You will need to be sure loading does not cause timing constraints to be violated. Reflections on stubs formed by combining two sections should watched for. \$\endgroup\$
    – Russell McMahon
    Commented Apr 13, 2012 at 17:21

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When you have two RAMs (of almost any variety), there are two choices:

  1. Width expansion; same address and control to both.
  2. Depth expansion; same address and data to both; separate chip selects.

What you propose is neither of these. You will have both chips driving the bus on reads, which isn't a good idea.

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