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Below part is quoted from the book "Beyond BIOS".

Each host bridge is represented in EFI as a device handle that contains a Device Path Protocol instance, and a protocol instance that abstracts the I/O operations that the host bus can perform. For example, a PCI Host Bus Controller supports the PCI Host Bridge I/O Protocol.

And below is the picture with the above quotation:

Figure 3.3 shows a platform with n CPUs, and a set of core chipset components that produce m host bridges.

enter image description here

I think the HB in the picture stands for Host Bridge. I know the Front Side Bus is a synonym of host bus. And bridge is a piece of hardware to connect different buses. So HB is the bridge to connect the host's bus, which is the FSB, to some other device buses, such as PCI.

But what does the Host Bus Controller mean? Where is it in the picture? I guess it's part of the HB/host bridge. Right?

And in the PCI scenario, does the communication flow go like this:

CPU -> FSB/Host Bus -> PCI Host Bus Controller -> PCI Host Bridge -> PCI bus -> PCI device

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Keep in mind the flow of information must follow the ISO 7 layers. You are mainly concerned here with the lowest level, i.e. the Physical Layer and that Protocols exist in each Layer, so all layers handle information but mainly Session and Physical layer for this context.

To avoid complications here is another simple model.

enter image description here

Read an overview on the OSI 7 layer model to get a broader perspective for any computer.

enter image description here

Regarding PC's

Communication Layers and Flow.

General comment: One cannot understand ANY meaning of "Bridge" unless you define the traffic and the Bus ( or physical carrier of data) on each side.

  • Just as Host can meaning anything until you define its "context" or frame of reference. Again refer to OSI 7 layers.

edit

  • A Host can be physical, logical, virtual, anything
  • An Adapter allows connection and communication from any target to another target. It must be specific and understand the Physical requirements and the protocols of any/every layer relevant to and from the target device.
  • This regardless if it is physical or virtual but enabled by the Host with higher level permissions. (e.g. USB-Serial, SCSI-PCI)
  • It may be integrated or broken down into "Functional blocks"
    • then it becomes a "HA" and may include a bus "bridge" , hence the names PCI Host bridge and SCSI HBA
    • thus the flow and logical/physical/functional blocks depends greatly on specific hardware and the intent of the explanation with respect to understanding.
      • as a smart phone is quite different from a motherboard.

A PCI Root Bridge is represented in UEFI as a device handle that contains a Device Path Protocol instance and a PCI Root Bridge Protocol instance.

"host controller, host adapter, or host bus adapter (HBA)" are all the same except historically HA's are closer to the target device and HC's is integrated and closer to the CPU. But this gets into design evolution from cards to chips to super IO chips.

USB3 is an evolution where targets can initiate traffic and connect target to target with permission from the CPU/OS/"User" privies etc.

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  • \$\begingroup\$ Thanks. I never expected OSI model can be applied here. It's refreshing. \$\endgroup\$ Apr 10 '17 at 8:56
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    \$\begingroup\$ I could have spent more time to ensure my definitions were strictly accurate and not so generalized with historical references but someone judged it a poor answer. A troll with no comment (-1) \$\endgroup\$ Apr 10 '17 at 12:11
  • \$\begingroup\$ That's unfortunate. It's helpful. But I need some more time to fully understand your anwser. \$\endgroup\$ Apr 10 '17 at 12:32
  • \$\begingroup\$ my 1st block diagram is most relevant to your question.. the rest is more generalized, For more details look at Intel and AMD chipsets which are different from a Snapdragon \$\endgroup\$ Apr 10 '17 at 12:34

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