Below part is quoted from the book "Beyond BIOS".
Each host bridge is represented in EFI as a device handle that contains a Device Path Protocol instance, and a protocol instance that abstracts the I/O operations that the host bus can perform. For example, a PCI Host Bus Controller supports the PCI Host Bridge I/O Protocol.
And below is the picture with the above quotation:
Figure 3.3 shows a platform with n CPUs, and a set of core chipset components that produce m host bridges.
I think the
HB in the picture stands for
Host Bridge. I know the
Front Side Bus is a synonym of
host bus. And
bridge is a piece of hardware to connect different buses. So
HB is the bridge to connect the host's bus, which is the
FSB, to some other device buses, such as PCI.
But what does the
Host Bus Controller mean? Where is it in the picture? I guess it's part of the
HB/host bridge. Right?
And in the PCI scenario, does the communication flow go like this:
CPU -> FSB/Host Bus -> PCI Host Bus Controller -> PCI Host Bridge -> PCI bus -> PCI device