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I would like to know is there any standard on placing capacitor on a pcb board. For example, in front of a power supply 3.3V, I put 100p, 10n, 10u, and 1n. How should I put it in the correct order from the nearest to the furthest from the specified pin. Is there any standard in this kind of placement. If possible can you attach a source to further increase my knowledge. I myself put it in order of 100p,1n,10n,and the furthest is 10u, however I do not really know whether this is correct or not. Thank you for your help.

Best regards,

RH

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    \$\begingroup\$ Without specifying the nature of the load and supply, it's difficult to answer. Decoupling capacitors are selected to reduce the supply impedance at a specific range of frequencies, determined by the needs of the load. Also, if you look at some impedance/frequency curves, I think you'll find that 10n/1n/100p aren't really helping much. Typically, in the context of high speed digital design, 100n 0402 ceramics get you the "middleish" frequencies, and a good stackup with good planes covers higher frequencies (100M+). However, this is a very complex subject. \$\endgroup\$ – uint128_t Apr 10 '17 at 15:20
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    \$\begingroup\$ If you have not watched it already, watch EEVBlog Dave's video about bypass caps: youtube.com/watch?v=BcJ6UdDx1vg There is no "standard" or "one size fits all". As everything in electronics: it depends. \$\endgroup\$ – Bimpelrekkie Apr 10 '17 at 15:31
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    \$\begingroup\$ Forget <10 nF unless you are making an RF amplifier. \$\endgroup\$ – winny Apr 10 '17 at 17:08
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    \$\begingroup\$ @winny And even then, a 10 nF capacitor will likely be useless due to parasitics. \$\endgroup\$ – uint128_t Apr 12 '17 at 0:46
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I've seen a lot of my fellow students and friend that are into electronics struggle with this, so I decided to type out a quite lengthy response - I hope people looking for similar information might find help in this.

We need to start with an understanding of what the decoupling capacitor is actually used for in the first place - many people will say that it is to filter out noise from other components. This is not the main/only reason, especially in digital circuits! If we have say a CMOS circuit, we will find that most of the current draw happens in very brief spikes on the clock. If we have no decoupling, this current will have to flow through the trace coming from the powersupply. This trace has a resistance R and inductance L. I have a schematic down lower where you can see these. When you have a sudden spike of current through this combination, we will have a large voltage drop over this trace, causing issues ranging from noise on mixed signal circuits, jitter on clocks, to complete failure of the device requiring a reset.

By placing a capacitor close to the pin, we have a local source of current during these spikes. On average, the capacitor will be charged from the powersupply. During the short current spikes, the capacitor will discharge, providing the current needed while doing so.

Now, on to the question:

It is a very common mistake to think that it's only the capacitance value that matters. The key is the combination of Equivalent Series Inductance (ESL) and capacitance. The equivalent schematic used in this post is the following:

Basic equivalent schematic for a capacitor

In this schematic, C is the rated capacitance. ESL is the equivalent inductance. This depends on the capacitor design, size, and type.

We often see something like this on our schematic:

schematic decouplingcapacitor ideal

When we place this on the pcb, it looks like this:

PCB decoupling capacitor

But when we look at the main non-idealities, the picture becomes more complex. We first need to replace our ideal capacitor with the circuit including the ESL. On top of that, we need to include the trace resistance and inductances. Our simple schematic is now:

Withnonidealities

Using a smaller capacitor with the same ESL closer to the part makes (almost - see (1)) no difference - in fact, it's performance might be worse! The reason we often want to use smaller capacitance values closer to the chip has to do with the fact that - in general - the ESL/ESR of these parts is lower (usually, we use smaller packages, as for a given family, these always have lower ESL).

The closer you can get it to the pin, the better, since the trace towards the pin also forms inductance and has a resistance. Note that it is not just the positive trace that matters - it is the inductance of the entire loop that matters - including the ground connection.

This Intersil appnote is a very good starting resource for more in depth information and figures. All figures that follow in this post are from this appnote.

http://www.intersil.com/content/dam/Intersil/documents/an13/an1325.pdf

If we factor in the impedance of a ideal capacitor, we know the impedance as a function of frequency has a \$\frac{1}{f}\$ behaviour - as we increase the frequency, the impedance decreases, and thus we get better filtering. However, every actual capacitor also has an ESL. If we include this ESL, and we look at the impedance of the capacitor as a function of frequency, we get the following picture:

enter image description here Source: Tamara Schmitz, Mike Wong, Intersil Application Note 1325: Choosing and Using Bypass Capacitors

So, what happens if we now get more capacitors? Let's say we choose a 1uF, 0.1uF and 0.01uF capacitor, in an 0805 formfactor. If we now put them together, we get the following plot:

enter image description here Source: Tamara Schmitz, Mike Wong, Intersil Application Note 1325: Choosing and Using Bypass Capacitors

What we see is that even though we added smaller capacitors, we don't really get any significant benefit - the inductance causes our impedance to go up, removing all benefit of the smaller capacitors.

What we should have done is use 3 different packages, say, 0805, 0603 and 0402. This would have given us the following figure:

enter image description here Source: Tamara Schmitz, Mike Wong, Intersil Application Note 1325: Choosing and Using Bypass Capacitors

(1)Ofcourse, since it's closer to the part there will be less trace inductance and resistance, but you might as well just put the bigger capacitance part closer, eliminating this difference

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    \$\begingroup\$ +1 for explaining the charge storage function of the decoupling capacitors and the effect of ESL, very often overlooked. \$\endgroup\$ – Enric Blanco Apr 10 '17 at 16:19
  • \$\begingroup\$ Or, just use one 1uF in 0402 package, right? \$\endgroup\$ – Timmy Brolin Apr 11 '19 at 10:22
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How should I put it in the correct order from the nearest to the furthest from the specified pin.

Generally you should put the lowest valued part, which you expect to provide the highest-frequency currents, closest to the chip. This minimizes the parasitic inductance between the chip and the capacitor, giving it the best chance to work at high frequencies.

I put 100p, 10n, 10u, and 1n.

I suspect that the 10 nF and 100 pF parts are counterproductive here. By pushing the higher valued parts farther away from the chip, they are degrading their performance, but they don't "store" enough charge to provide meaningful current for many loads. In particular I'll suggest very strongly if the chip being bypassed is a digital device, you'd be better off getting rid of the lower valued capacitors and moving the higher valued capacitors closer.

Of course every application is different. In an analog application you might have a very good idea of what frequency band the IC will draw currents in and a low-valued cap might be a better choice.

You should also be aware that capacitors in parallel with values separated by more than about one decade (i.e. the larger part is more than 10x the value of the smaller part) have a good chance of producing an anti-resonant (or parallel resonance) behavior where the impedance is very high at some frequency between the series resonant frequencies of the two parts. This is discussed in detail in section 3.5 of Murata's Application Manual for Power Supply Noise Suppression and Decoupling for Digital ICs

See also: Will a 0402 0.01 µF ceramic capacitor next to a 0402 0.1 µF ceramic capacitor have any power decoupling benefits?

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  • \$\begingroup\$ +1 for the warning about anti-resonances. They're very often overlooked when discussing about capacitive decoupling. \$\endgroup\$ – Enric Blanco Apr 10 '17 at 16:11
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    \$\begingroup\$ I’d like to add: The caps should be “electrically” close to the chip’s power supply pins. This means short traces to both the Vdd and GND pins. \$\endgroup\$ – Michael Dec 26 '17 at 9:42
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Silicon circuits only work at speed, because of the ONCHIP stored energy. An MCU may have 1nF or 2nF or 100nF onchip, mostly in well_substrate capacitors; wells exist under every Pchannel FET in standard processes; the distributed nature, usually in tiny rectangles, of these wells, along with the even smaller "contacts" into the well and nearby "contacts" into that substrate underlying the well, lead to substantial resistance for charge to flow in and out of the well_sub capacitor.

But you have a well under every Pch FET, thus a well is needed in every inverter, bigger well in every gate, even bigger well in every FlipFLop, on and on. With capacitance and resistance and as "joren vaes" illustrated, the always present inductance.

With 100,000 of these tiny (2u by 5u, for example) capacitors all over the silicon, there is lots of capacitance because the Cs add up. The Rs reduce, because in parallel. And the inductances reduce, because in parallel.

It gets even better. All those gates and FFs, with lots of tiny FET gate oxide capacitors, also store change in gate-capacitors; any gateC that is not changing state is usefully storing charge, to be used by the sibling transistors just 1micron away, or 10microns away.

And there is some metal-metal capacitance, if VDD is atop GND metal.

All three --- well_substrate caps, gate_oxide_caps, metal_metal caps ---- are in parallel. Perhaps 0.1uF (100,000 picoFarad).

Then the MCU clocks, and 100,000 gates simultaneously demand charge, and as the Pch and Nch transistors switch oppositely there is the crossover time when both transistors are ON for say oh hmmm 20picoseconds. Passing 20uA for 20pS. Not all 1,000,000 gates, but just 100,000 gates this time. What does that do to the onchip stored charge.

Assuming Q = I * T = 20uA for 20pS, Q = 400 e-18 coulombs, scaled up by 100,000 gates. Equals 400-13 or 40 picoCoulombs. To be supplied ONCHIP. In 20pS. What happens?

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