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I'm going to be designing a discrete delta-sigma ADC to be built on a PCB. I think I understand the basic concept, but I will need to order components fairly soon. Here's my problem: while I have learned about op-amp/comparator parameters, I don't know which parameters I should prioritize when choosing parts for my application.

The design I'm considering will look something like this: Basic Delta-Sigma ADC Schematic

  • Since the op-amp is configured as an integrator, input offset voltage/current could be a major problem.
    • I'm currently considering using a TL07x-series op-amp.
    • Would the DC offsets of this device be problematic?
  • When choosing comparators, should I be more concerned about propagation delay, hysteresis, or input offsets? I am currently considering the LM393, KA319, and the LM311.
  • What other considerations should I take into account? Are my concerns even warranted, considering that my goal is not a high-performance device?

Notes:

  • I will be manually soldering the PCB, meaning that I would prefer DIP packages, though I can work with SOIC.
  • My goal is to get a working design, it does not need to have high accuracy.
  • The device does not need to operate at high frequencies, though something that can work at (44.1ksps or higher) would be nice.

Summary: I am wondering if the input offsets introduced by both the op-amp and the comparator at the input stage will cause the integrator to drift significantly, or if the capacitor will be charged/discharged quickly enough for errors introduced from DC offsets to be negligible.

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  • \$\begingroup\$ QFN's are actually surprisingly easy to solder while using flux, I'd pic some components and simulate this in LT spice \$\endgroup\$ – Voltage Spike Apr 11 '17 at 19:39
  • \$\begingroup\$ Breadboard-able chips might be a good choice - at least until a working version is achieved. If you desire 44.1ksps, clk will be much faster, so high-speed digital components required. You're using a comparator as D-to-A: perhaps you should use a bipolar type like KA319,LM311 not single-ended LM393. \$\endgroup\$ – glen_geek Apr 11 '17 at 21:00
  • \$\begingroup\$ @glen_geek I don't get the second part of your comment. All of the comparators I linked are differential, bipolar devices with common-collector outputs. \$\endgroup\$ – Caleb Reister Apr 12 '17 at 0:29
  • \$\begingroup\$ Inputs are differential, but LM393 has output referred to its ground pin. Am guessing you want the D-to-A comparator output switching between some +V and -V ? \$\endgroup\$ – glen_geek Apr 12 '17 at 0:40
  • \$\begingroup\$ @glen_geek To be honest, I didn't think of that. I could see how that would help for the upper-right comparator in my schematic (it could potentially drain the capacitor faster), but a comparator switching between + and -V would be problematic for the flip-flop. \$\endgroup\$ – Caleb Reister Apr 12 '17 at 0:44
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The biggest factor is your quantization noise for resolution.

Since you have not given any specs, a priority to Vio and Iio offsets circuit balance , noise rejection, crosstalk, signal bandwidth and decimation ratio precise suggestions are not possible. (hence you must always start ANY design with a Great Spec)

However to achieve the performance of commercial IC's you must have many loops and higher order integration to move the quantization noise far above the signal bandwidth. Using a circuit that integrates twice instead of just once is a great way to lower the modulator’s in-band quantization noise.

For instance, Texas Instruments DS converters include second- through sixth-order modulators. Multi-order modulators shape the quantization noise to even higher frequencies than do the lower-order modulators.

ref: read Texas Instruments, Nuts and Bolts of the Delta-Sigma Video Tutorial [Online]. Available: http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=WEB408001

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  • \$\begingroup\$ That is good advice. I probably do need to solidify my spec. I made this post at a fairly early point in my research. I have since read about the noise shaping characteristics of Delta-Sigma ADCs, and have decided that it is impractical to implement one in the time I have. Therefore, I've switched to a dual-slope design. The integrator may still be a problem though. \$\endgroup\$ – Caleb Reister Apr 15 '17 at 16:57
  • \$\begingroup\$ P.S. The link doesn't work. \$\endgroup\$ – Caleb Reister Apr 15 '17 at 16:58

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