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I have recently started studying RS flip-flops. I noticed that for the SR NOR Flip-Flops most of the images online, as well as my text, have the 'Set' input attached to the NOR gate that outputs 'not-Q', some sources said that it is designed this way because we want Q to be '1' when S is pulsed '1' and vice versa.

enter image description here

However when dealing with NAND SR Flip Flops this rule of making Q '1' by pulsing S to '1' does not work. Futhermore some of the online images of NAND SR Flip-Flops have the 'Set' input on the gate that outputs Q and others have the 'Set' input on the gate that outputs the compliment of Q.

enter image description here

Please excuse my rather elaborate question but in summary, I would like to know: 1) Does the R and S inputs have to be attached to specific gates in the flip-flop. 2) If yes to '1)' can someone please explain why this is, for both the NAND and NOR SR Flip-Flop.

Thank you in advance.

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    \$\begingroup\$ Related: SR Flip-Flop: NOR or NAND? \$\endgroup\$ – The Photon Apr 12 '17 at 1:34
  • \$\begingroup\$ It sounds like you understand the concept well enough to see the inconsistencies in the notation. By my reckoning you can now pass any test on the subject. BTW, for the NAND RS Flip-Flop, consider inverting the R and S inputs. That is, make them active low. Now the NAND RS Flip-Flop will set the Q output high when you "activate" the S input. For this reason, you may see yet another notation where there is a bar over the top of the "R" and "S" inputs. \$\endgroup\$ – st2000 Apr 12 '17 at 1:37
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As suggested in the comments, for the NAND RS Flip-Flop, consider inverting the R and S inputs.

Additionally, it may help your understanding if you consider the SR NAND flip-flop with the deMorgan's symbols for NANDs, emphasizing the active input negative state.

SR NAND with deMorgans gates

Either input 0, causes a 1 output.

On the SR NOR flip-flop, either input 1, causes a 0 output.

If you compare the two flip-flops, the logic symbols are now forms of OR's (one a negative-OR and the other a NOR).

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schematic

simulate this circuit – Schematic created using CircuitLab

Consider NOR gate first: labeling which inputs is R or S is completely arbitrary. Once it was decided, try to decide which output is Q. Let's choose R on the top gate and S on the bottom gate. NOR gate is an active high circuit, a high input uniquely determines its low output. Consider R = 1 which clears the top gate output so the corresponding output in the top gate must be Q, not Q'. Otherwise, it clears Q' contradicts to the definition of R which clears Q. Similarly, S = 1 clears the lower gate output. The lower gate output must be Q', not Q. Otherwise, it clears Q contradicting to the definition of S which sets Q.

Once we understand the NOR operations, NAND gate operations can be argued similarly. But there is a more elegant approach. It uses duality principle and De Morgan theorem to convert from a latch in NOR/NOR configuration to its dual in NAND/NAND configuration. The principle states switching a circuit to its dual, you simply swap the inputs and outputs with their complements. Therefore, a NOR/NOR configuration flip-flop with R and Q on top gate, S and Q' on bottom gate corresponds to a NAND/NAND configuration flip-flop with R' and Q' on top gate, S' and Q on bottom gate.

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