I have recently started studying RS flip-flops. I noticed that for the SR NOR Flip-Flops most of the images online, as well as my text, have the 'Set' input attached to the NOR gate that outputs 'not-Q', some sources said that it is designed this way because we want Q to be '1' when S is pulsed '1' and vice versa.
However when dealing with NAND SR Flip Flops this rule of making Q '1' by pulsing S to '1' does not work. Futhermore some of the online images of NAND SR Flip-Flops have the 'Set' input on the gate that outputs Q and others have the 'Set' input on the gate that outputs the compliment of Q.
Please excuse my rather elaborate question but in summary, I would like to know: 1) Does the R and S inputs have to be attached to specific gates in the flip-flop. 2) If yes to '1)' can someone please explain why this is, for both the NAND and NOR SR Flip-Flop.
Thank you in advance.