SR NAND and NOR Flip-Flops [duplicate]

Question

I have recently started studying RS flip-flops. I noticed that for the SR NOR Flip-Flops most of the images online, as well as my text, have the 'Set' input attached to the NOR gate that outputs 'not-Q', some sources said that it is designed this way because we want Q to be '1' when S is pulsed '1' and vice versa.

However when dealing with NAND SR Flip Flops this rule of making Q '1' by pulsing S to '1' does not work. Futhermore some of the online images of NAND SR Flip-Flops have the 'Set' input on the gate that outputs Q and others have the 'Set' input on the gate that outputs the compliment of Q.

Please excuse my rather elaborate question but in summary, I would like to know: 1) Does the R and S inputs have to be attached to specific gates in the flip-flop. 2) If yes to '1)' can someone please explain why this is, for both the NAND and NOR SR Flip-Flop.

Thank you in advance.

Answer 1

As suggested in the comments, for the NAND RS Flip-Flop, consider inverting the R and S inputs.

Additionally, it may help your understanding if you consider the SR NAND flip-flop with the deMorgan's symbols for NANDs, emphasizing the active input negative state.

Either input 0, causes a 1 output.

On the SR NOR flip-flop, either input 1, causes a 0 output.

If you compare the two flip-flops, the logic symbols are now forms of OR's (one a negative-OR and the other a NOR).

Answer 2

^{simulate this circuit – Schematic created using CircuitLab}

Consider NOR gate first: labeling which inputs is R or S is completely arbitrary. Once it was decided, try to decide which output is Q. Let's choose R on the top gate and S on the bottom gate. NOR gate is an active high circuit, a high input uniquely determines its low output. Consider R = 1 which clears the top gate output so the corresponding output in the top gate must be Q, not Q'. Otherwise, it clears Q' contradicts to the definition of R which clears Q. Similarly, S = 1 clears the lower gate output. The lower gate output must be Q', not Q. Otherwise, it clears Q contradicting to the definition of S which sets Q.

Once we understand the NOR operations, NAND gate operations can be argued similarly. But there is a more elegant approach. It uses duality principle and De Morgan theorem to convert from a latch in NOR/NOR configuration to its dual in NAND/NAND configuration. The principle states switching a circuit to its dual, you simply swap the inputs and outputs with their complements. Therefore, a NOR/NOR configuration flip-flop with R and Q on top gate, S and Q' on bottom gate corresponds to a NAND/NAND configuration flip-flop with R' and Q' on top gate, S' and Q on bottom gate.