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I did some changes to a design in Quartus and in Qsys. Now when I load the design to my FPGA with Quartus programmer then I get a message about opencores and that there is unlimited time. The msg was not there with the original design.

Why does it appear and what are the limitations the msg is mentioning?

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Altera allows evaluation of it's IP cores using what it calls an OpenCores Plus evaluation license.

The message this means is that you are using an IP core in your design for which you have not purchased a license (probably NIOS based on your other question), and as such Quartus compiled the design based on the evaluation license.

The terms of the license say that you are allowed to test the core, and you can use the compiled sof file for as long as you want, so long as it is connected to the computer that compiled it via JTAG.

If you disconnect the board from the computer, it will continue to run for as far as I recall up to 1 hour. After an hour the license expires and the unlicensed core will go into reset until you either power cycle the design, or connect it back to the computer that compiled it.

The original SOF file was, again guessing based on your question, compiled by Terasic who will have purchased a license for each of the IP cores they are using. This means that the original file was compiled with a full license not an evaluation license, so the timeout protection is disabled.

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